公开(公告)号：US20130309805A1

公开(公告)日：2013-11-21

申请号：US13737127

申请日：2013-01-09

Applicant: INTERMOLECULAR, INC.

Inventor： Haifan Liang ,  Sang Lee ,  Wei Liu ,  Sandeep Nijhawan ,  Jeroen Van Duren

IPC: H01L31/18

CPC classification number: H01L31/065 ,  H01L31/0322 ,  H01L31/18 ,  H01L31/1864 ,  Y02E10/50 ,  Y02E10/541

Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25-0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.

公开(公告)号：US20130309804A1

公开(公告)日：2013-11-21

申请号：US13711860

申请日：2012-12-12

Applicant: INTERMOLECULAR, INC.

Inventor： Haifan Liang ,  Sang Lee ,  Wei Liu ,  Sandeep Nijhawan ,  Jeroen Van Duren

IPC: H01L31/18

CPC classification number: H01L31/065 ,  H01L31/0322 ,  H01L31/18 ,  H01L31/1864 ,  Y02E10/50 ,  Y02E10/541

Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25−0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.

Abstract translation: 一种制造高效CIGS太阳能电池的方法，包括从约25原子％至约66原子％之间的Ga浓度的溅射靶中沉积Ga浓度（Ga /（Ga + In）= 0.25-0.66）。 此外，该方法包括与导致高效率的高温退火工艺相结合的高温硒化工艺。

公开(公告)号：US09034690B2

公开(公告)日：2015-05-19

申请号：US14133421

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Zhi-Wen Sun

IPC: H01L21/16 ,  H01L21/306 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/465 ,  H01L21/70

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof.

Abstract translation: 本文所述的实施方案提供了形成铟镓锌氧化物（IGZO）器件的方法。 提供基板。 在基板上形成IGZO层。 在IGZO层上形成含铜层。 在含铜层上进行湿式蚀刻处理，以在IGZO层上形成源极区域和漏极区域。 在含铜层上执行湿法蚀刻工艺包括将含铜层暴露于包括过氧化物化合物和柠檬酸，甲酸，丙二酸，乳酸，依替膦酸，膦酸或其中的一种的蚀刻溶液 其组合。

公开(公告)号：US09012261B2

公开(公告)日：2015-04-21

申请号：US14094379

申请日：2013-12-02

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L21/02 ,  H01L21/465 ,  H01L21/70 ,  H01L27/12

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅电极沉积，栅极电极图案化，栅极介电沉积，栅极电介质图案化，金属基半导体材料（例如IGZO）沉积，金属基半导体材料（例如IGZO）图案化，蚀刻停止 沉积，蚀刻停止构图，源极/漏极沉积，源极/漏极图案化，钝化沉积或钝化图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US20140273340A1

公开(公告)日：2014-09-18

申请号：US14094379

申请日：2013-12-02

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅电极沉积，栅极电极图案化，栅极介电沉积，栅极电介质图案化，金属基半导体材料（例如IGZO）沉积，金属基半导体材料（例如IGZO）图案化，蚀刻停止 沉积，蚀刻停止构图，源极/漏极沉积，源极/漏极图案化，钝化沉积或钝化图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US20150279674A1

公开(公告)日：2015-10-01

申请号：US14511475

申请日：2014-10-10

Applicant: Intermolecular, Inc.

Inventor： Seon-Mee Cho ,  Sang Lee ,  Minh Huu Le

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/04 ,  C23C14/14

CPC classification number: H01L21/02631 ,  C23C14/0036 ,  C23C14/086 ,  C23C14/352 ,  C23C14/562 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/7869

Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The third target includes a compound of indium oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, when deposited at room temperature, without the need of a subsequent anneal treatment.

Abstract translation: 使用共溅射技术使用PVD沉积In-Ga-Zn-O膜。 膜在包括氧和氩的气氛中沉积。 约300℃的加热器设定值导致衬底温度为约165℃。一个靶包括In，Ga，Zn和O的合金，原子比为In：Ga：Zn为约1:1:1的原子比。 第二靶标包括氧化锌的化合物。 第三靶包括氧化铟的化合物。 当在室温下沉积时，膜以沉积状态呈现c轴对准的结晶（CAAC）相，而不需要随后的退火处理。

公开(公告)号：US09105527B2

公开(公告)日：2015-08-11

申请号：US14135086

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le

IPC: H01L21/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/465 ,  H01L21/66

CPC classification number: H01L27/1259 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/465 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅极介电沉积，栅极电介质图案化，基于金属的半导体沉积，基于金属的图案化，蚀刻停止沉积，蚀刻停止图案化，源极/漏极沉积或源极/漏极图案化中的至少一个。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US09105526B2

公开(公告)日：2015-08-11

申请号：US14134571

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Minh Huu Le ,  Sang Lee ,  Jeroen Van Duren

IPC: H01L21/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/66

CPC classification number: H01L21/02565 ,  H01L21/02554 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78693

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅极介电沉积，栅极电介质图案化，金属基半导体（例如ZnO x，ZnSnO x，ZnInO x或ZnGaO x）沉积，金属基半导体（例如ZnO x，ZnSnO x，ZnInO x或ZnGaO x）中的至少一种， 图案化，蚀刻停止沉积，蚀刻停止图案化，源极/漏极沉积或源极/漏极图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US08859405B2

公开(公告)日：2014-10-14

申请号：US13711860

申请日：2012-12-12

Applicant: Intermolecular, Inc.

Inventor： Haifan Liang ,  Sang Lee ,  Wei Liu ,  Sandeep Nijhawan ,  Jeroen Van Duren

IPC: H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01L31/18 ,  H01L31/065

CPC classification number: H01L31/065 ,  H01L31/0322 ,  H01L31/18 ,  H01L31/1864 ,  Y02E10/50 ,  Y02E10/541

Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25−0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.

Abstract translation: 一种制造高效CIGS太阳能电池的方法，包括从约25原子％至约66原子％之间的Ga浓度的溅射靶中沉积Ga浓度（Ga /（Ga + In）= 0.25-0.66）。 此外，该方法包括与导致高效率的高温退火工艺相结合的高温硒化工艺。

公开(公告)号：US20140273341A1

公开(公告)日：2014-09-18

申请号：US14133421

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Zhi-Wen Sun

IPC: H01L21/465 ,  H01L21/70 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof.

Abstract translation: 本文所述的实施方案提供了形成铟镓锌氧化物（IGZO）器件的方法。 提供基板。 在基板上形成IGZO层。 在IGZO层上形成含铜层。 在含铜层上进行湿式蚀刻处理，以在IGZO层上形成源极区域和漏极区域。 在含铜层上执行湿法蚀刻工艺包括将含铜层暴露于包括过氧化物化合物和柠檬酸，甲酸，丙二酸，乳酸，依替膦酸，膦酸或其中的一种的蚀刻溶液 其组合。