公开(公告)号：US20170117030A1

公开(公告)日：2017-04-27

申请号：US15019788

申请日：2016-02-09

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40626 ,  G11C11/4087 ,  G11C29/025 ,  G11C29/06 ,  G11C29/789 ,  G11C2029/0403

Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.

公开(公告)号：US10262717B2

公开(公告)日：2019-04-16

申请号：US15803710

申请日：2017-11-03

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/02 ,  G11C29/06 ,  G11C29/00 ,  G11C29/04

Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.

公开(公告)号：US10164633B2

公开(公告)日：2018-12-25

申请号：US15645125

申请日：2017-07-10

Applicant: Invensas Corporation

Inventor： Curtis Dicke ,  George Courville ,  David Edward Fisch ,  Randall Sandusky ,  Kent Stalnaker

IPC: H03L5/00 ,  H03K19/00 ,  H01C10/50 ,  G11C7/10 ,  H03F3/45

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

公开(公告)号：US09299398B2

公开(公告)日：2016-03-29

申请号：US14683687

申请日：2015-04-10

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C5/14 ,  G11C7/00 ,  G11C29/52 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.