-
公开(公告)号：US20160055816A1
公开(公告)日：2016-02-25
申请号：US14930160
申请日：2015-11-02
Inventor： Toshio MIYAZAWA , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
-
公开(公告)号：US20190088225A1
公开(公告)日：2019-03-21
申请号：US16161909
申请日：2018-10-16
Applicant: Japan Display Inc.
Inventor： Takayuki SUZUKI , Hiroyuki ABE , Masahiro Maki , Mitsuru Goto
IPC: G09G3/36 , G06F3/044 , G06F3/041 , G02F1/1333 , G02F1/1362 , G02F1/1335 , G02F1/133
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
-
公开(公告)号：US10134351B2
公开(公告)日：2018-11-20
申请号：US15898272
申请日：2018-02-16
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G06F3/044 , G09G3/36 , G06F3/041 , G02F1/133 , G02F1/1333 , G02F1/1335 , G02F1/1362
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
-
公开(公告)号：US20180102103A1
公开(公告)日：2018-04-12
申请号：US15830061
申请日：2017-12-04
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Hideo Sato , Hiroaki Komatsu
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period t apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
-
公开(公告)号：US09892704B2
公开(公告)日：2018-02-13
申请号：US15611995
申请日：2017-06-02
Inventor： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
-
Patent Agency Ranking
公开(公告)号：US09704447B2
公开(公告)日：2017-07-11
申请号：US15227015
申请日：2016-08-03
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G06F3/044 , G09G3/36 , G06F3/041 , G02F1/133 , G02F1/1333 , G02F1/1335
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
-
公开(公告)号：US09697790B2
公开(公告)日：2017-07-04
申请号：US15255338
申请日：2016-09-02
Inventor： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
-
公开(公告)号：US09542897B2
公开(公告)日：2017-01-10
申请号：US14805134
申请日：2015-07-21
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Hideo Sato , Hiroaki Komatsu
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
Abstract translation: 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。
-
公开(公告)号：US09460679B2
公开(公告)日：2016-10-04
申请号：US14930160
申请日：2015-11-02
Inventor： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
-
公开(公告)号：US20150054804A1
公开(公告)日：2015-02-26
申请号：US14526807
申请日：2014-10-29
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes a substrate having an image display area, pixel electrodes formed in the image display area of the substrate, a common electrode formed in the image display area of the substrate, inside signal lines formed inside the image display area of the substrate and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area of the substrate and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area of the substrate and electrically connected to the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines include a first portion, and a second portion that is higher in electric resistance than an electric resistance of the first portion, and the second portion has a bend.
Abstract translation: 显示装置包括具有图像显示区域的基板，形成在基板的图像显示区域中的像素电极，形成在基板的图像显示区域中的公共电极，形成在基板的图像显示区域内的信号线内部;以及 电连接到像素电极，形成在基板的图像显示区域外部并电连接到内部信号线的外部信号线，以及形成在基板的图像显示区域的内部和外部的公共线，并且电连接到公共电极 。 在内部信号线和公共电极之间形成耦合电容。 外部信号线包括第一部分和电阻高于第一部分的电阻的第二部分，并且第二部分具有弯曲部。
-
-
-
-
-
-
-
-
-
Search Results
39
records
(took 0.03 seconds)
