公开(公告)号：US20080120523A1

公开(公告)日：2008-05-22

申请号：US11561010

申请日：2006-11-17

申请人： Jason A. Cox ,  Keith A. DeWeese ,  Robert J. Dorsey ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

发明人： Jason A. Cox ,  Keith A. DeWeese ,  Robert J. Dorsey ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

IPC分类号： G06F11/30

CPC分类号： G06F11/3636

摘要： A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

摘要翻译： 一种用于从非并发事件创建跟踪触发的方法和系统，所述系统包括：跟踪触发机制，包括：多个多路复用器，用于将多个信号分解成多组信号; 用于匹配多个信号以形成多个事件的模式匹配机制，以及跟踪阵列触发控制块，以对多个独立控制的事件执行一个或多个功能，以便从非并发事件创建灵活的跟踪触发控制 以控制诸如用于捕获跟踪数据的数据收集功能的启动和停止。

公开(公告)号：US08938588B2

公开(公告)日：2015-01-20

申请号：US12969617

申请日：2010-12-16

申请人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/084

摘要： Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.

摘要翻译： 确保共享缓存中令牌所需的高速缓存操作的进展，包括：侦听执行令牌所需缓存操作的指令; 确定窥探机是否可用，并且窥探机被设置为预约状态; 如果窥探机可用并且窥探机器处于预约状态，则确定执行令牌所需高速缓存操作的指令是否拥有令牌或是联合指令; 如果指令是联合指令，指示操作重试; 如果执行令牌需要的缓存操作的指令拥有一个令牌，则调度一个缓存控制器; 确定相关计算节点的所有需要​​的高速缓存控制器是否可用于执行指令; 如果所需的高速缓存控制器可用，则执行指令，否则不执行指令。

公开(公告)号：US08576599B2

公开(公告)日：2013-11-05

申请号：US13364607

申请日：2012-02-02

申请人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

发明人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

IPC分类号： G11C15/00 ,  G11C5/14

CPC分类号： H01L25/18 ,  G06F12/0895 ,  G06F12/1027 ,  G11C15/00 ,  G11C15/04 ,  H01L27/1203 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。

公开(公告)号：US20120159640A1

公开(公告)日：2012-06-21

申请号：US12969634

申请日：2010-12-16

申请人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F21/24

CPC分类号： G06F21/335

摘要： Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

摘要翻译： 获取对令牌控制的系统资源的访问，包括：由令牌代理接收需要访问令牌控制的系统资源的命令，其中令牌代理是用于获取令牌的自动计算机器，并将命令分发给令牌控制系统 执行资源 由所述令牌代理识别第一需求状态，所述第一需求状态指示所述令牌代理需要访问所述令牌经纪人不具有令牌的令牌受控系统资源; 由令牌代理请求可配置数量的令牌以获得对令牌控制的系统资源的访问，而不调度用于执行该命令的操作处理器，直到获取至少一个令牌; 由令牌代理将所获取的令牌分配给操作处理程序; 并由令牌代理分派操作处理程序及其分配的用于执行命令的令牌。

公开(公告)号：US20120159087A1

公开(公告)日：2012-06-21

申请号：US12969617

申请日：2010-12-16

申请人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/084

摘要： Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.

摘要翻译： 确保共享缓存中令牌所需的高速缓存操作的进展，包括：侦听执行令牌所需缓存操作的指令; 确定窥探机是否可用，并且窥探机被设置为预约状态; 如果窥探机可用并且窥探机器处于预约状态，则确定执行令牌所需高速缓存操作的指令是否拥有令牌或是联合指令; 如果指令是联合指令，指示操作重试; 如果执行令牌需要的缓存操作的指令拥有一个令牌，则调度一个缓存控制器; 确定相关计算节点的所有需要​​的高速缓存控制器是否可用于执行指令; 如果所需的高速缓存控制器可用，则执行指令，否则不执行指令。

公开(公告)号：US20080091883A1

公开(公告)日：2008-04-17

申请号：US11548820

申请日：2006-10-12

申请人： Jason A. Cox ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

发明人： Jason A. Cox ,  Eric F. Robinson ,  Thuong Q. Truong ,  Mark J. Wolski

IPC分类号： G06F12/00

CPC分类号： G06F12/0857 ,  G06F12/0855

摘要： A system for detecting and breaking up requester starvation, including: a plurality of logic circuits, each of the plurality of logic circuits permitted to access a cache via a plurality of requesters for requesting information from the cache; and a counter for counting a number of times each of the plurality of requestors of each of the plurality of logic circuits has (i) successfully accessed one or more of a plurality of arbitration levels and (ii) has been rejected by a subsequent arbitration level; wherein when the counter reaches a predetermined threshold value, an event is triggered to block a first type of requester from accessing the cache and to permit a second type of requester to access the cache; and wherein the counter is reconfigured to count a predetermined number of cycles before the first type of requester is unblocked from accessing the cache.

摘要翻译： 一种用于检测和分解请求者饥饿的系统，包括：多个逻辑电路，所述多个逻辑电路中的每一个允许经由多个请求者访问高速缓存，用于从高速缓存请求信息; 以及用于计数多个逻辑电路中的每一个的多个请求者中的每一个的次数的计数器，其具有（i）成功访问多个仲裁级别中的一个或多个，并且（ii）已被随后的仲裁级别拒绝 ; 其中当所述计数器达到预定阈值时，触发事件以阻止第一类型的请求者访问所述高速缓存并且允许第二类型的请求者访问所述高速缓存; 并且其中所述计数器被重新配置为在所述第一类型的请求者被解除阻塞以访问所述高速缓存之前对预定数量的周期进行计数。

公开(公告)号：US08707449B2

公开(公告)日：2014-04-22

申请号：US12969634

申请日：2010-12-16

申请人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Kevin C. Lin ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F21/24

CPC分类号： G06F21/335

摘要： Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

摘要翻译： 获取对令牌控制的系统资源的访问，包括：由令牌代理接收需要访问令牌控制的系统资源的命令，其中令牌代理是用于获取令牌的自动计算机器，并将命令分发给令牌控制系统 执行资源 由所述令牌代理识别第一需求状态，所述第一需求状态指示所述令牌代理需要访问所述令牌经纪人不具有令牌的令牌受控系统资源; 由令牌代理请求可配置数量的令牌以获得对令牌控制的系统资源的访问，而不调度用于执行该命令的操作处理器，直到获取至少一个令牌; 由令牌代理将所获取的令牌分配给操作处理程序; 并由令牌代理分派操作处理程序及其分配的用于执行命令的令牌。

公开(公告)号：US08671247B2

公开(公告)日：2014-03-11

申请号：US12967086

申请日：2010-12-14

申请人： Jason A. Cox ,  Kevin C K Lin ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Kevin C K Lin ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F13/00

CPC分类号： G06F12/0833 ,  G06F12/0811

摘要： An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

摘要翻译： 用于将入站总线操作传送到处理器侧处理机的L2高速缓存，方法和计算机程序产品。 该方法包括接收通过系统互连接收的入站总线操作的总线操作处理机，总线操作处理机识别将完成总线操作的处理器侧处理机的需求操作，总线操作处理机器发送所识别的需求 对处理器侧处理机进行操作，以及执行所识别的需求操作的处理器侧处理机。

公开(公告)号：US20120159082A1

公开(公告)日：2012-06-21

申请号：US12969651

申请日：2010-12-16

申请人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0877 ,  Y02D10/13

摘要： Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

摘要翻译： 公开了用于直接访问高速缓冲存储器的方法和装置。 实施例包括由连接到用于高速缓存存储器的高速缓存控制器的直接访问管理器接收描述要对高速缓存存储器执行的区域范围零操作的区域范围零命令; 响应于接收到区域范围零命令，生成直接存储器访问区域范围零命令，直接存储器访问区域范围零命令具有操作代码和操作所在的高速缓冲存储器的物理地址的标识 执行 将直接存储器访问区范围零命令发送到高速缓存存储器的高速缓存控制器; 并且由缓存控制器根据操作代码和高速缓冲存储器的物理地址的识别来执行直接存储器访问区域范围零操作。

公开(公告)号：US20120151142A1

公开(公告)日：2012-06-14

申请号：US12967086

申请日：2010-12-14

申请人： Jason A. Cox ,  Kevin CK Lin ,  Eric F. Robinson ,  Mark J. Wolski

发明人： Jason A. Cox ,  Kevin CK Lin ,  Eric F. Robinson ,  Mark J. Wolski

IPC分类号： G06F13/36 ,  G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/0811

摘要： An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

摘要翻译： 用于将入站总线操作传送到处理器侧处理机的L2高速缓存，方法和计算机程序产品。 该方法包括接收通过系统互连接收的入站总线操作的总线操作处理机，总线操作处理机识别将完成总线操作的处理器侧处理机的需求操作，总线操作处理机器发送所识别的需求 对处理器侧处理机进行操作，以及执行所识别的需求操作的处理器侧处理机。