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公开(公告)号：US20090305462A1
公开(公告)日：2009-12-10
申请号：US12542235
申请日：2009-08-17
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。
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公开(公告)号：US08513791B2
公开(公告)日：2013-08-20
申请号：US11750631
申请日：2007-05-18
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。
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公开(公告)号：US20120127771A1
公开(公告)日：2012-05-24
申请号：US13364607
申请日：2012-02-02
IPC分类号： G11C15/04 , H01L21/8239
CPC分类号： H01L25/18 , G06F12/0895 , G06F12/1027 , G11C15/00 , G11C15/04 , H01L27/1203 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。
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公开(公告)号：US08576599B2
公开(公告)日：2013-11-05
申请号：US13364607
申请日：2012-02-02
CPC分类号： H01L25/18 , G06F12/0895 , G06F12/1027 , G11C15/00 , G11C15/04 , H01L27/1203 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。
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公开(公告)号：US20080291767A1
公开(公告)日：2008-11-27
申请号：US11751315
申请日：2007-05-21
IPC分类号： G11C8/00 , H01L21/4763
CPC分类号： H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203
摘要： A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer.
摘要翻译： 提供多端口寄存器文件（例如，存储器元件），其中寄存器堆的每个读端口位于主数据存储元件上方和/或下方的单独晶片中。 这在本发明中通过利用三维积分来实现，其中多个有源电路层被垂直堆叠并且使用垂直排列的互连将装置从堆叠层之一连接到另一层叠层中的另一装置。
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公开(公告)号：US08343814B2
公开(公告)日：2013-01-01
申请号：US12542235
申请日：2009-08-17
IPC分类号： H01L21/335
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。
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公开(公告)号：US20080288720A1
公开(公告)日：2008-11-20
申请号：US11750676
申请日：2007-05-18
IPC分类号： G06F12/00 , G11C15/04 , H01L21/8239
CPC分类号： H01L25/18 , G06F12/0895 , G06F12/1027 , G11C15/00 , G11C15/04 , H01L27/1203 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。
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公开(公告)号：US20080283995A1
公开(公告)日：2008-11-20
申请号：US11750631
申请日：2007-05-18
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中通过利用三维积分来实现，其中多个有源电路层是垂直堆叠的并且垂直对准的互连被用于将设备从堆叠层之一连接到另一层叠层中的另一个设备 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。
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