公开(公告)号：US08850095B2

公开(公告)日：2014-09-30

申请号：US13023141

申请日：2011-02-08

申请人： Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Eric F. Robinson

发明人： Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Eric F. Robinson

IPC分类号： G06F13/00 ,  G06F15/16

CPC分类号： G06F13/00 ,  G06F13/1657 ,  G06F13/37

摘要： A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).

摘要翻译： 一种用于检测利用最小逻辑资源的环形互连中的事务的活动锁定/饥饿的新颖且有用的成本有效的机制。 而不是在环中同时监视所有事务，机制仅监视环中的单个事务。 采样点位于环中的一个包含一组N个锁存器的点上。 如果监控的事务没有被饿死，则它被释放，并且检测逻辑以循环方式在下一候选事务上移动。 如果被监控的事务通过采样点一个阈值次数，则认为它是饥饿的，并且激活了一个饥饿预防处理过程。 通过遍历整个环一次一个交易，所有的饥饿交易最终将被检测到O（N2）的检测时间的上限。

公开(公告)号：US08352646B2

公开(公告)日：2013-01-08

申请号：US12969651

申请日：2010-12-16

申请人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

IPC分类号： G06F13/28

CPC分类号： G06F12/084 ,  G06F12/0877 ,  Y02D10/13

摘要： Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

摘要翻译： 公开了用于直接访问高速缓冲存储器的方法和装置。 实施例包括由连接到用于高速缓存存储器的高速缓存控制器的直接访问管理器接收描述要对高速缓存存储器执行的区域范围零操作的区域范围零命令; 响应于接收到区域范围零命令，生成直接存储器访问区域范围零命令，直接存储器访问区域范围零命令具有操作代码和操作所在的高速缓冲存储器的物理地址的标识 执行 将直接存储器访问区范围零命令发送到高速缓存存储器的高速缓存控制器; 并且由缓存控制器根据操作代码和高速缓冲存储器的物理地址的识别来执行直接存储器访问区域范围零操作。

公开(公告)号：US09298460B2

公开(公告)日：2016-03-29

申请号：US13305760

申请日：2011-11-29

申请人： Revital Eres ,  Amit Golander ,  Nadav Levison ,  Sagi Manole ,  Ayal Zaks

发明人： Revital Eres ,  Amit Golander ,  Nadav Levison ,  Sagi Manole ,  Ayal Zaks

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30123 ,  G06F9/384

摘要： Systems and methods are disclosed for enhancing the throughput of a processor by minimizing the number of transfers of data associated with data transfer between a register file and a memory stack. The register file used by a processor running an application is partitioned into a number of blocks. A subset of the blocks of the register file is defined in an application binary interface enabling the subset to be pre-allocated and exposed to the application binary interface. Optionally, blocks other than the subset are not exposed to the application binary interface so that the data relating to application function switch or a context switch is not transferred between the unexposed blocks and a memory stack.

摘要翻译： 公开了用于通过最小化与寄存器文件和存储器堆栈之间的数据传输相关联的数据传送的数量来增强处理器的吞吐量的系统和方法。 运行应用程序的处理器使用的寄存器文件被分割成多个块。 在应用程序二进制接口中定义了寄存器文件块的一个子集，使子集能够被预分配并暴露给应用程序二进制接口。 可选地，除子集之外的块不暴露于应用二进制接口，使得与应用功能切换或上下文切换有关的数据不在未暴露的块和存储器堆之间传送。

公开(公告)号：US20130151818A1

公开(公告)日：2013-06-13

申请号：US13323933

申请日：2011-12-13

申请人： Erez Barak ,  Alejandro Rico Carro ,  Jeffrey H. Derby ,  Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Sagi Manole ,  Robert K. Montoye

发明人： Erez Barak ,  Alejandro Rico Carro ,  Jeffrey H. Derby ,  Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Sagi Manole ,  Robert K. Montoye

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/35 ,  G06F9/3826

摘要： A method and system for improving performance and latency of instruction execution within an execution pipeline in a processor. The method includes finding, while decoding an instruction, a pointer register used by the instruction; reading the pointer register; validating a pointer register entry; reading, if the pointer register entry is valid, a register file entry; validating a register file entry; validating, if the register file entry is invalid, a valid register file entry wherein the valid register file entry is in the register file's future file; bypassing, if the valid register file entry is valid, a valid register file value from the register file's future file to the execution pipeline wherein the valid register file value is in the valid register file entry; and executing the instruction using the valid register file value; wherein at least one of the steps is carried out using a computer device.

摘要翻译： 一种用于改善处理器中的执行流水线内的指令执行的性能和延迟的方法和系统。 该方法包括在解码指令时发现指令使用的指针寄存器; 读指针寄存器; 验证指针寄存器条目; 如果指针寄存器条目有效，读取寄存器文件条目; 验证注册文件条目; 如果注册文件条目无效，验证有效的注册文件条目，其中有效的注册文件条目在注册文件的未来文件中; 绕过，如果有效的注册文件条目有效，则从注册文件的未来文件到执行管道的有效注册文件值，其中有效的注册文件值在有效的注册文件条目中; 并使用有效的寄存器文件值执行指令; 其中使用计算机设备执行所述步骤中的至少一个。

公开(公告)号：US20130138922A1

公开(公告)日：2013-05-30

申请号：US13305760

申请日：2011-11-29

申请人： Revital Eres ,  Amit Golander ,  Nadav Levison ,  Sagi Manole ,  Ayal Zaks

发明人： Revital Eres ,  Amit Golander ,  Nadav Levison ,  Sagi Manole ,  Ayal Zaks

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/312

CPC分类号： G06F9/30123 ,  G06F9/384

摘要： Systems and methods are disclosed for enhancing the throughput of a processor by minimizing the number of transfers of data associated with data transfer between a register file and a memory stack. The register file used by a processor running an application is partitioned into a number of blocks. A subset of the blocks of the register file is defined in an application binary interface enabling the subset to be pre-allocated and exposed to the application binary interface. Optionally, blocks other than the subset are not exposed to the application binary interface so that the data relating to application function switch or a context switch is not transferred between the unexposed blocks and a memory stack.

摘要翻译： 公开了用于通过最小化与寄存器文件和存储器堆栈之间的数据传输相关联的数据传送的数量来增强处理器的吞吐量的系统和方法。 运行应用程序的处理器使用的寄存器文件被分割成多个块。 在应用程序二进制接口中定义了寄存器文件块的一个子集，使子集能够被预分配并暴露给应用程序二进制接口。 可选地，除子集之外的块不暴露于应用二进制接口，使得与应用功能切换或上下文切换有关的数据不在未暴露的块和存储器堆之间传送。

公开(公告)号：US20120203946A1

公开(公告)日：2012-08-09

申请号：US13023141

申请日：2011-02-08

申请人： Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Eric F. Robinson

发明人： Amit Golander ,  Omer Heymann ,  Nadav Levison ,  Eric F. Robinson

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G06F13/1657 ,  G06F13/37

摘要： A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).

摘要翻译： 一种用于检测利用最小逻辑资源的环形互连中的事务的活动锁定/饥饿的新颖且有用的成本有效的机制。 而不是在环中同时监视所有事务，机制仅监视环中的单个事务。 采样点位于环中的一个包含一组N个锁存器的点上。 如果监控的事务没有被饿死，则它被释放，并且检测逻辑以循环方式在下一候选事务上移动。 如果被监控的事务通过采样点一个阈值次数，则认为它是饥饿的，并且激活了一个饥饿预防处理过程。 通过遍历整个环一次一个交易，所有的饥饿交易最终将被检测到O（N2）的检测时间的上限。

公开(公告)号：US20120159082A1

公开(公告)日：2012-06-21

申请号：US12969651

申请日：2010-12-16

申请人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

发明人： Jason A. Cox ,  Omer Heymann ,  Nadav Levison ,  Kevin C. Lin ,  Eric F. Robinson

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0877 ,  Y02D10/13

摘要： Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

摘要翻译： 公开了用于直接访问高速缓冲存储器的方法和装置。 实施例包括由连接到用于高速缓存存储器的高速缓存控制器的直接访问管理器接收描述要对高速缓存存储器执行的区域范围零操作的区域范围零命令; 响应于接收到区域范围零命令，生成直接存储器访问区域范围零命令，直接存储器访问区域范围零命令具有操作代码和操作所在的高速缓冲存储器的物理地址的标识 执行 将直接存储器访问区范围零命令发送到高速缓存存储器的高速缓存控制器; 并且由缓存控制器根据操作代码和高速缓冲存储器的物理地址的识别来执行直接存储器访问区域范围零操作。