Protection of a program against a trap
    11.
    发明申请
    Protection of a program against a trap 有权
    保护针对陷阱的程序

    公开(公告)号:US20070220612A1

    公开(公告)日:2007-09-20

    申请号:US11717225

    申请日:2007-03-13

    CPC classification number: G06F21/52 G06F21/77

    Abstract: A method for controlling the execution, by a central processing unit, of a program stored in a memory, a redundancy code stored with first current data at a current address being assigned to second subsequent data of the program and depending at least on the second data.

    Abstract translation: 一种用于通过中央处理单元执行存储在存储器中的程序执行的方法,所述冗余代码被存储在当前地址处的第一当前数据,并被分配给所述程序的第二后续数据,并且至少依赖于所述第二数据 。

    DEVICE FOR DISTURBING THE OPERATION OF AN INTEGRATED CIRCUIT
    15.
    发明申请
    DEVICE FOR DISTURBING THE OPERATION OF AN INTEGRATED CIRCUIT 有权
    用于扰乱集成电路运行的装置

    公开(公告)号:US20120261594A1

    公开(公告)日:2012-10-18

    申请号:US13444349

    申请日:2012-04-11

    Abstract: A system for injecting faults by laser beams into an electronic circuit including: at least two lasers capable of emitting approximately parallel beams; at least one optical system receiving, on the magnifying side, the beams; and a support of the integrated circuit placed on the reducing side of the optical system.

    Abstract translation: 一种用于通过激光束将故障注入电子电路的系统,包括:至少两个能够发射大致平行光束的激光器; 至少一个光学系统,在所述放大侧上接收所述光束; 以及放置在光学系统的减少侧的集成电路的支撑。

    VERIFICATION OF DATA READ IN MEMORY
    17.
    发明申请
    VERIFICATION OF DATA READ IN MEMORY 有权
    内存中数据读取的验证

    公开(公告)号:US20100325320A1

    公开(公告)日:2010-12-23

    申请号:US12743684

    申请日:2008-10-18

    CPC classification number: G06F21/606 G06F21/755

    Abstract: A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.

    Abstract translation: 一种用于检查在电路和处理单元之间传送的数据的方法和电路,其中:从电路发出的数据通过第一缓冲元件,该第一缓冲元件的尺寸是要随后传送的数据的大小的倍数 总线处理单元; 由电路处理单元提供的地址暂时存储在第二元件中; 并且将第一元素的内容与来自电路的当前数据进行比较,至少当它们对应于已经存在于该第一元素中的数据的地址时。

    INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS
    18.
    发明申请
    INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS 有权
    双线总线和单线总线之间的接口

    公开(公告)号:US20100017553A1

    公开(公告)日:2010-01-21

    申请号:US12502634

    申请日:2009-07-14

    CPC classification number: G06F13/4282 G06F13/4027 G06F2213/0016

    Abstract: A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.

    Abstract translation: 一种用于将包括至少数据线和时钟线的第一总线转换成单线总线的方法和装置,其中第一总线的数据位在时钟信号的半个周期上被转换,以在第二总线上传输第二总线 公共汽车,在另一半期间,等待方式被放置在第二辆公共汽车上。

    Integrated circuit test simulator
    19.
    发明申请
    Integrated circuit test simulator 审中-公开
    集成电路测试模拟器

    公开(公告)号:US20070083351A1

    公开(公告)日:2007-04-12

    申请号:US11546509

    申请日:2006-10-11

    CPC classification number: G01R31/318342

    Abstract: A method and a simulator for testing an electronic circuit by parallel execution of a program in the circuit and in a simulator, including a step of checking that commands and conditions contained in the simulator have effectively been executed during the test.

    Abstract translation: 一种用于通过并行执行电路和模拟器中的程序来测试电子电路的方法和仿真器,包括在测试期间有效地执行包含在模拟器中的命令和条件的步骤。

    NON-VOLATILE MEMORY COUNTER
    20.
    发明申请
    NON-VOLATILE MEMORY COUNTER 有权
    非易失性存储器计数器

    公开(公告)号:US20130028369A1

    公开(公告)日:2013-01-31

    申请号:US13560476

    申请日:2012-07-27

    CPC classification number: H03K21/00 G11C16/349 H03K21/403

    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

    Abstract translation: 包括至少两个子计数器的非易失性存储器中的计数器,每个副计数器以不同的模计数,在单个子计数器上传送的计数器的增量和子计数器依次递增。

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