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    Apparatus having a screened structure for detecting thermal radiation
    11.
    发明授权
    Apparatus having a screened structure for detecting thermal radiation 有权
    具有用于检测热辐射的屏蔽结构的装置

    公开(公告)号：US08575550B2

    公开(公告)日：2013-11-05

    申请号：US12808745

    申请日：2008-07-30

    Applicant: Jeffrey Wright

    Inventor： Jeffrey Wright

    IPC: H01L31/0203

    CPC classification number: G01J5/04 ,  G01J5/0285 ,  G01J5/045 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus for detecting radiation has a substrate, a protective housing fitting on the substrate, which has an electrically conductive material and a top facing away from the substrate, and that has an aperture therein. A stack is fitted on the substrate inside the protective housing and includes at least one detector substrate having at least one thermal detector element thereon that converts incoming thermal radiation into an electrical signal, at least one circuit carrier having at least one read circuit for reading out the electrical signal, and at least one cover that covers the detector element. The detector substrate is located between the circuit substrate and the cover. The detector substrate and the cover are arranged on each other such that the detector element of the detector substrate and the cover have at least one first stack cavity of the stack therebetween, the stack cavity being defined by the detector support and the cover. The circuit substrate and the detector substrate are arranged on each other such that the detector substrate and the circuit substrate have at least one second stack cavity therebetween, the second stack cavity being defined by the circuit substrate and the detector substrate. At least one of the first stack cavity and the second stack cavity is evacuated. The stack top that faces the substrate is accessible from outside of the protective housing.

    Abstract translation: 用于检测辐射的装置具有衬底，衬底上的保护壳体配件，其具有导电材料和背离衬底的顶部，并且其中具有孔。 堆叠被安装在保护壳体内的衬底上，并且包括至少一个检测器衬底，其上具有至少一个热检测器元件，其将进入的热辐射转换成电信号，至少一个电路载体具有至少一个用于读出的读取电路 电信号和覆盖检测器元件的至少一个盖。 检测器基板位于电路基板和盖子之间。 检测器基板和盖彼此布置，使得检测器基板和盖的检测器元件具有其间的堆叠的至少一个第一堆叠空腔，堆叠腔由检测器支撑件和盖限定。 电路基板和检测器基板彼此布置，使得检测器基板和电路基板之间具有至少一个第二堆叠空腔，第二堆叠腔由电路基板和检测器基板限定。 将第一堆叠腔和第二堆叠腔中的至少一个排空。 面向基板的堆叠顶部可从保护外壳的外部进入。

    Coding and marking printing system
    12.
    发明授权
    Coding and marking printing system 有权
    编码和打标系统

    公开(公告)号：US08322806B2

    公开(公告)日：2012-12-04

    申请号：US12513045

    申请日：2007-10-30

    Applicant: Jeffrey Wright ,  Daniel Kent ,  Mark Van Vegten

    Inventor： Jeffrey Wright ,  Daniel Kent ,  Mark Van Vegten

    IPC: B41J29/38

    CPC classification number: B41J2/005

    Abstract: A method and device for coding and marking printing including defining a print image in dot formation of various sizes and locations; determining and providing a set of individual print control instructions for individually controlling a plurality of dot image print head nozzles to form the defined print image at absolute dot positions; and undertaking the individual control instructions to provide a printed image on a printing substrate corresponding to the defined print image, whereby the system allows for calculated adjustment of each dot position without computational limitation during the printing cycle.

    Abstract translation: 一种用于编码和标记印刷的方法和装置，包括以各种尺寸和位置的点形成定义印刷图像; 确定和提供一组单独的打印控制指令，用于单独控制多个点图像打印头喷嘴，以在绝对点位置形成所定义的打印图像; 并且进行单独的控制指令以在对应于所定义的打印图像的打印基板上提供打印图像，由此系统允许在打印周期期间对计算的每个点位置的调整而没有计算限制。

    Memory device and method having multiple address, data and command buses
    14.
    发明授权
    Memory device and method having multiple address, data and command buses 失效
    具有多个地址，数据和命令总线的存储器件和方法

    公开(公告)号：US07548483B2

    公开(公告)日：2009-06-16

    申请号：US11900296

    申请日：2007-09-10

    Applicant: James Cullum ,  Jeffrey Wright

    Inventor： James Cullum ,  Jeffrey Wright

    IPC: G11C8/00

    CPC classification number: G11C8/12 ,  G11C7/1012 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/107

    Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

    Abstract translation: 动态随机存取存储器（“DRAM”）器件包括一对内部地址总线，其通过地址多路复用器选择性地耦合到外部地址总线，以及一对内部数据总线，其通过以下方式选择性地耦合到外部数据总线 数据多路复用器。 DRAM设备还包括用于每一组存储器单元的存储体多路复用器，其将内部地址总线和内部数据总线中的一个选择性地耦合到相应存储单元组。 选择由命令解码器产生的信号使得多路复用器响应于命令解码器接收的每个存储器命令来选择备用的内部地址和数据总线。

    Memory array decoder
    16.
    发明申请
    Memory array decoder 有权

    公开(公告)号：US20070121417A1

    公开(公告)日：2007-05-31

    申请号：US11698503

    申请日：2007-01-26

    Applicant: Christopher Morzano ,  Jeffrey Wright

    Inventor： Christopher Morzano ,  Jeffrey Wright

    IPC: G11C8/00

    CPC classification number: G11C8/10 ,  G11C11/4087 ,  G11C29/844

    Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

    MEMORY ARRAY DECODER
    17.
    发明申请
    MEMORY ARRAY DECODER 有权
    内存阵列解码器

    公开(公告)号：US20060007762A1

    公开(公告)日：2006-01-12

    申请号：US10887616

    申请日：2004-07-09

    Applicant: Christopher Morzano ,  Jeffrey Wright

    Inventor： Christopher Morzano ,  Jeffrey Wright

    IPC: G11C29/00

    CPC classification number: G11C8/10 ,  G11C11/4087 ,  G11C29/844

    Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

    Abstract translation: 一种用于选择存储设备中的存储位置的装置和方法，包括接收预解码位置地址信号，匹配信号和冗余位置地址使能信号中的至少一个，使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号，所述解码器响应于所述预解码的位置地址信号，并且其中所述冗余解码器可操作以产生用于 选择第二位置，所述冗余解码器响应于所述冗余位置地址使能信号，并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。

    Individual I/O modulation in memory devices
    18.
    发明申请
    Individual I/O modulation in memory devices 失效
    存储设备中的单独I / O调制

    公开(公告)号：US20050169068A1

    公开(公告)日：2005-08-04

    申请号：US10766004

    申请日：2004-01-29

    Applicant: Mehul Nagrani ,  Victor Wong ,  Jeffrey Wright

    Inventor： Mehul Nagrani ,  Victor Wong ,  Jeffrey Wright

    IPC: G11C7/00 ,  G11C7/08

    CPC classification number: G11C7/08

    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

    Abstract translation: 一种具有降低功耗的DRAM电路，在某些情况下，存储器阵列存取速度更快。 与阈值电容/长度相比，根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输入/输出线比比阈值更长，更容性的输入/输出线被感测得更早。 由于更短的输入/输出线路被更快地感测到，所以它们需要更少的功率并且可以更快地访问。

    Ammunition feeder
    19.
    发明申请
    Ammunition feeder 失效
    弹药进料器

    公开(公告)号：US20050081420A1

    公开(公告)日：2005-04-21

    申请号：US10672594

    申请日：2003-09-27

    Applicant: Jeffrey Wright

    Inventor： Jeffrey Wright

    IPC: F41A9/29 ,  F42B39/08

    CPC classification number: F42B39/08

    Abstract: Ammunition feeder with a handle portion and a head portion. The handle portion is integrally attached to the head portion. The handle portion is a flat elongate shape having raised portions to help the user maintain his grip on the handle. The head portion is shaped to accept the front end of a standard ammunition belt. The head is flattened longitudinally on one side and includes a longitudinal recess so that the feed pawl on a standard machine gun is not activated by the head. A preferred embodiment includes that the feeder fits with the M 60 machine gun and the 240 Golf machine gun.

    Abstract translation: 具有把手部分和头部的弹药进料器。 手柄部分一体地附接到头部。 手柄部分是具有凸起部分的平坦的细长形状，以帮助使用者保持对手柄的握持。 头部被成形为接受标准弹药带的前端。 头部在一侧纵向扁平化并且包括纵向凹槽，使得标准机枪上的进给爪不被头部激活。 一个优选实施例包括进料器与M 60机枪和240高尔夫机枪配合。

    Infrared light sensor having a high signal voltage and a high signal/noise ratio
    20.
    发明授权
    Infrared light sensor having a high signal voltage and a high signal/noise ratio 有权
    红外光传感器具有高信号电压和高信噪比

    公开(公告)号：US08963087B2

    公开(公告)日：2015-02-24

    申请号：US13264908

    申请日：2010-04-16

    Applicant: Carsten Giebeler ,  Jeffrey Wright ,  Tim Chamberlain

    Inventor： Carsten Giebeler ,  Jeffrey Wright ,  Tim Chamberlain

    IPC: G01J5/34 ,  G01J5/08

    CPC classification number: G01J5/34 ,  G01J5/08 ,  G01J5/0846

    Abstract: An infrared light sensor for an infrared light detector (1), including a substrate membrane section (2) and at least two sensor chips (7 to 10), which are fastened next to each other on the substrate membrane section (2) and each comprise a layer element (11) which is produced from pyroelectrically sensitive material and is electrically contacted by a base electrode (12) and a head electrode (13) and is arranged in such that there is a voltage difference in each case between the head electrode (13) and the base electrode (12) of each layer element (11) when the layer elements (11) are irradiated with infrared light; and a coupling line (14 to 16) in each case for two adjacently arranged sensor chips (7 to 10), the coupling line coupling the head electrode (13) of the one sensor chip (7 to 9) and the base electrode (12) of the other sensor chip (8 to 10) to each other in an electrically conductive manner so that the layer elements (11) of the sensor chips (7 to 10) are connected in a series circuit, which has one of the base electrodes (17) at one end thereof and one of the head electrodes (18) at the other end thereof, at which a total voltage difference of the series circuit can be tapped as the sum of the individual voltage differences of the layer elements (11).

    Abstract translation: 一种用于红外光检测器（1）的红外光传感器，包括基板膜部分（2）和至少两个传感器芯片（7至10），它们在基板膜部分（2）上彼此紧固并且每个 包括由热敏材料制成并与基底电极（12）和头部电极（13）电接触的层元件（11），并且被布置成使得在每个情况下在头部电极之间存在电压差 （11）被红外线照射时，各层元件（11）的基极（13）和基极（12） 和连接线（14〜16），用于两个相邻布置的传感器芯片（7至10），耦合线将一个传感器芯片（7至9）的头部电极（13）和基极（12） ）以使得传感器芯片（7至10）的层元件（11）连接在串联电路中，该串联电路具有一个基极电极 （17）和其另一端的头电极（18）中的一个，串联电路的总电压差可以抽头作为层元件（11）的各个电压差之和， 。

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