公开(公告)号：US20100165028A1

公开(公告)日：2010-07-01

申请号：US12513045

申请日：2007-10-30

Applicant: Jeffrey Wright ,  Daniel Kent ,  Mark Van Vegten

Inventor： Jeffrey Wright ,  Daniel Kent ,  Mark Van Vegten

IPC: B41J29/38

CPC classification number: B41J2/005

Abstract: A method and device for coding and marking printing including defining a print image in dot formation of various sizes and locations; determining and providing a set of individual print control instructions for individually controlling a plurality of dot image print head nozzles to form the defined print image at absolute dot positions; and undertaking the individual control instructions to provide a printed image on a printing substrate corresponding to the defined print image, whereby the system allows for calculated adjustment of each dot position without computational limitation during the printing cycle.

Abstract translation: 一种用于编码和标记印刷的方法和装置，包括以各种尺寸和位置的点形成定义印刷图像; 确定和提供一组单独的打印控制指令，用于单独控制多个点图像打印头喷嘴，以在绝对点位置形成所定义的打印图像; 并且进行单独的控制指令以在对应于所定义的打印图像的打印基板上提供打印图像，由此系统允许在打印周期期间对计算的每个点位置的调整而没有计算限制。

公开(公告)号：US20070263459A1

公开(公告)日：2007-11-15

申请号：US11432421

申请日：2006-05-10

Applicant: Kang Kim ,  Jeffrey Wright

Inventor： Kang Kim ,  Jeffrey Wright

IPC: G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1069 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

Abstract: An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by generating a first variable count in response to comparing a reference voltage to a first voltage at a calibration terminal when an external load is connected. A first pull-up impedance circuit is varied in response to a first variable count and varying an impedance in a second variable pull-up impedance circuit in response to the first variable count. A second variable count is generated responsive to comparing the reference voltage to a second voltage at a reference node between the second variable pull-up impedance circuit and a serially connected to a variable pull-down impedance circuit. The impedance to the variable pull-down impedance circuit is varied in response to the second variable count. The first and second variable counts for configuring the output drivers are output when a steady state is achieved.

Abstract translation: 输出驱动器校准电路确定用于配置可调阻抗输出驱动器的校准值。 当外部负载连接时，响应于将参考电压与校准端子处的第一电压进行比较，产生第一变量计数来校准输出驱动器。 第一上拉阻抗电路响应于第一可变计数而变化，并响应于第一可变计数改变第二可变上拉阻抗电路中的阻抗。 响应于将参考电压与第二可变上拉阻抗电路与串联连接到可变下拉阻抗电路的参考节点处的第二电压进行比较而产生第二可变计数。 可变下拉阻抗电路的阻抗响应于第二可变计数而变化。 当实现稳定状态时，输出用于配置输出驱动器的第一个和第二个变量计数。

公开(公告)号：US20070028027A1

公开(公告)日：2007-02-01

申请号：US11190370

申请日：2005-07-26

Applicant: Jeff Janzen ,  Jeffrey Wright ,  James Cullum

Inventor： Jeff Janzen ,  Jeffrey Wright ,  James Cullum

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G06F13/1684 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4093 ,  G11C2207/107

Abstract: A synchronous dynamic random access memory (“SDRAM”) device includes several banks of memory cell coupled to a read data path and a write data path. The read data path includes a read latch that stores a relatively large number of read data bits received in parallel from a bank of memory cells. Groups of the stored read data bits are sequentially selected by a multiplexer and applied to a read data bus. Groups of write data bits are sequentially coupled to the SDRAM device through a write data bus that is separate from the read data bus, and they are sequentially stored in input registers. When the input registers are full, the write data bits are coupled in parallel to a bank of memory cells. The number of bits in the write data bus is preferably a submultiple of the number of bits in the read data bus.

Abstract translation: 同步动态随机存取存储器（“SDRAM”）器件包括耦合到读取数据路径和写入数据路径的若干存储单元组。 读数据路径包括读存储器，其存储从一组存储器单元并行接收的相对大量的读数据位。 存储的读取数据位的组由多路复用器依次选择并应用于读取数据总线。 写数据位组通过与读数据总线分离的写数据总线顺序地耦合到SDRAM器件，并且它们被依次存储在输入寄存器中。 当输入寄存器满时，写数据位并联耦合到一组存储单元。 写数据总线中的比特数优选地是读数据总线中的比特数的数量。

公开(公告)号：US20120132807A1

公开(公告)日：2012-05-31

申请号：US13264908

申请日：2010-04-16

Applicant: Carsten Giebeler ,  Jeffrey Wright ,  Tim Chamberlain

Inventor： Carsten Giebeler ,  Jeffrey Wright ,  Tim Chamberlain

IPC: G01J5/10

CPC classification number: G01J5/34 ,  G01J5/08 ,  G01J5/0846

Abstract: An infrared light sensor for an infrared light detector (1), including a substrate membrane section (2) and at least two sensor chips (7 to 10), which are fastened next to each other on the substrate membrane section (2) and each comprise a layer element (11) which is produced from pyroelectrically sensitive material and is electrically contacted by a base electrode (12) and a head electrode (13) and is arranged in such that there is a voltage difference in each case between the head electrode (13) and the base electrode (12) of each layer element (11) when the layer elements (11) are irradiated with infrared light; and a coupling line (14 to 16) in each case for two adjacently arranged sensor chips (7 to 10), the coupling line coupling the head electrode (13) of the one sensor chip (7 to 9) and the base electrode (12) of the other sensor chip (8 to 10) to each other in an electrically conductive manner so that the layer elements (11) of the sensor chips (7 to 10) are connected in a series circuit, which has one of the base electrodes (17) at one end thereof and one of the head electrodes (18) at the other end thereof, at which a total voltage difference of the series circuit can be tapped as the sum of the individual voltage differences of the layer elements (11).

Abstract translation: 一种用于红外光检测器（1）的红外光传感器，包括基板膜部分（2）和至少两个传感器芯片（7至10），它们在基板膜部分（2）上彼此紧固并且每个 包括由热敏材料制成并与基底电极（12）和头部电极（13）电接触的层元件（11），并且被布置成使得在每个情况下在头部电极之间存在电压差 （11）被红外线照射时，各层元件（11）的基极（13）和基极（12） 和连接线（14〜16），用于两个相邻布置的传感器芯片（7至10），耦合线将一个传感器芯片（7至9）的头部电极（13）和基极（12） ）以使得传感器芯片（7至10）的层元件（11）连接在串联电路中，该串联电路具有一个基极电极 （17）和其另一端的头电极（18）中的一个，串联电路的总电压差可以抽头作为层元件（11）的各个电压差之和， 。

公开(公告)号：US20110024628A1

公开(公告)日：2011-02-03

申请号：US12808745

申请日：2008-07-30

Applicant: Jeffrey Wright

Inventor： Jeffrey Wright

IPC: H01L31/0203

CPC classification number: G01J5/04 ,  G01J5/0285 ,  G01J5/045 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus for detecting radiation has a substrate, a protective housing fitting on the substrate, which has an electrically conductive material and a top facing away from the substrate, and that has an aperture therein. A stack is fitted on the substrate inside the protective housing and includes at least one detector substrate having at least one thermal detector element thereon that converts incoming thermal radiation into an electrical signal, at least one circuit carrier having at least one read circuit for reading out the electrical signal, and at least one cover that covers the detector element. The detector substrate is located between the circuit substrate and the cover. The detector substrate and the cover are arranged on each other such that the detector element of the detector substrate and the cover have at least one first stack cavity of the stack therebetween, the stack cavity being defined by the detector support and the cover. The circuit substrate and the detector substrate are arranged on each other such that the detector substrate and the circuit substrate have at least one second stack cavity therebetween, the second stack cavity being defined by the circuit substrate and the detector substrate. At least one of the first stack cavity and the second stack cavity is evacuated. The stack top that faces the substrate is accessible from outside of the protective housing.

Abstract translation: 用于检测辐射的装置具有衬底，衬底上的保护壳体配件，其具有导电材料和背离衬底的顶部，并且其中具有孔。 堆叠被安装在保护壳体内的衬底上，并且包括至少一个检测器衬底，其上具有至少一个热检测器元件，其将进入的热辐射转换成电信号，至少一个电路载体具有至少一个用于读出的读取电路 电信号和覆盖检测器元件的至少一个盖。 检测器基板位于电路基板和盖子之间。 检测器基板和盖彼此布置，使得检测器基板和盖的检测器元件具有其间的堆叠的至少一个第一堆叠空腔，堆叠腔由检测器支撑件和盖限定。 电路基板和检测器基板彼此布置，使得检测器基板和电路基板之间具有至少一个第二堆叠空腔，第二堆叠腔由电路基板和检测器基板限定。 将第一堆叠腔和第二堆叠腔中的至少一个排空。 面向基板的堆叠顶部可从保护外壳的外部进入。

公开(公告)号：US20100082293A1

公开(公告)日：2010-04-01

申请号：US12567465

申请日：2009-09-25

Applicant: Edward P. Mitchell ,  Joseph Fouad ,  Jeffrey Wright

Inventor： Edward P. Mitchell ,  Joseph Fouad ,  Jeffrey Wright

IPC: G06F15/00 ,  G06F17/40 ,  G08B21/00

CPC classification number: G05B19/0428 ,  G05B19/4183 ,  G05B2219/31217 ,  G05B2219/31282 ,  G05B2219/31318

Abstract: Techniques are disclosed for providing robust, comprehensive measurement and analysis for optimizing efficiency of compressed air systems. The techniques provided can be implemented, for example, in a network appliance local to the target compressed air system, and/or in a server configured to remotely monitor and evaluate the target system. On-site data logging as well as on-site or remote data analysis can be enabled, along with onboard data consolidation. Meters (e.g., airflow, air pressure, power, and/or acoustic) are deployed at the target system and provide data upon which the analysis is based.

Abstract translation: 公开了用于提供强大的综合测量和分析以优化压缩空气系统的效率的技术。 所提供的技术可以例如在目标压缩空气系统本地的网络设备中和/或被配置为远程监视和评估目标系统的服务器中实现。 可以启用现场数据记录以及现场或远程数据分析，以及板载数据整合。 仪表（例如气流，空气压力，功率和/或声学）部署在目标系统处，并提供基于分析的数据。

公开(公告)号：US07283418B2

公开(公告)日：2007-10-16

申请号：US11190270

申请日：2005-07-26

Applicant: James Cullum ,  Jeffrey Wright

Inventor： James Cullum ,  Jeffrey Wright

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/1012 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/107

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

Abstract translation: 动态随机存取存储器（“DRAM”）器件包括一对内部地址总线，其通过地址多路复用器选择性地耦合到外部地址总线，以及一对内部数据总线，其通过以下方式选择性地耦合到外部数据总线 数据多路复用器。 DRAM设备还包括用于每一组存储器单元的存储体多路复用器，其将内部地址总线和内部数据总线中的一个选择性地耦合到相应存储单元组。 选择由命令解码器产生的信号使得多路复用器响应于命令解码器接收的每个存储器命令来选择备用的内部地址和数据总线。

公开(公告)号：US20070025173A1

公开(公告)日：2007-02-01

申请号：US11190270

申请日：2005-07-26

Applicant: James Cullum ,  Jeffrey Wright

Inventor： James Cullum ,  Jeffrey Wright

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/1012 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/107

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

公开(公告)号：US20060254954A1

公开(公告)日：2006-11-16

申请号：US11127378

申请日：2005-05-12

Applicant: Jeffrey Wright

Inventor： Jeffrey Wright

IPC: B65D5/50

CPC classification number: B65D5/5016 ,  B65D5/4204

Abstract: A carton has a display window that allows a premium article mounted within the carton to be viewed from the exterior of the carton.

Abstract translation: 一个纸箱有一个显示窗口，允许从纸箱的外部看到安装在纸箱内的优质物品。

公开(公告)号：US20060171219A1

公开(公告)日：2006-08-03

申请号：US11316377

申请日：2005-12-22

Applicant: Christopher Morzano ,  Jeffrey Wright

Inventor： Christopher Morzano ,  Jeffrey Wright

IPC: G11C29/00

CPC classification number: G11C8/10 ,  G11C11/4087 ,  G11C29/844

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract translation: 一种用于选择存储设备中的存储位置的装置和方法，包括接收预解码位置地址信号，匹配信号和冗余位置地址使能信号中的至少一个，使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号，所述解码器响应于所述预解码的位置地址信号，并且其中所述冗余解码器可操作以产生用于 选择第二位置，所述冗余解码器响应于所述冗余位置地址使能信号，并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。