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19 条记录 (耗时 0.027 秒)

    Defect Detection on Characteristically Capacitive Circuit Nodes
    11.
    发明申请
    Defect Detection on Characteristically Capacitive Circuit Nodes 有权
    特征电容电路节点的缺陷检测

    公开(公告)号：US20130229189A1

    公开(公告)日：2013-09-05

    申请号：US13411068

    申请日：2012-03-02

    申请人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

    发明人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

    IPC分类号： G01R31/14

    CPC分类号： G01R31/3008

    摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

    摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。

    Defect detection on characteristically capacitive circuit nodes
    14.
    发明授权
    Defect detection on characteristically capacitive circuit nodes 有权
    特征电容电路节点的缺陷检测

    公开(公告)号：US08860425B2

    公开(公告)日：2014-10-14

    申请号：US13411068

    申请日：2012-03-02

    申请人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

    发明人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

    IPC分类号： G01R31/14

    CPC分类号： G01R31/3008

    摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

    摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。

    Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network
    15.
    发明授权
    Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network 有权
    通过短时钟网络同步3D堆叠集成电路中的全局时钟

    公开(公告)号：US08525569B2

    公开(公告)日：2013-09-03

    申请号：US13217335

    申请日：2011-08-25

    申请人： Thomas J. Bucelot ,  Liang-Teck Pang ,  Phillip J. Restle

    发明人： Thomas J. Bucelot ,  Liang-Teck Pang ,  Phillip J. Restle

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10 ,  H01L24/16 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2224/81 ,  H01L2924/00

    摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

    摘要翻译： 提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。 在两个或更多个层中的每一个上，时钟分配网络包括具有多个扇区的时钟网格，用于向各种芯片位置提供全局时钟信号，用于驱动时钟网格的多级缓冲时钟树，并且至少包括 根和多个时钟缓冲器，以及用于将全局时钟信号提供给缓冲的时钟树的至少一部分的一个或多个多路复用器。 两个或更多个层中的每一个上的多个时钟缓冲器中的至少一些时钟缓冲器的输入使用芯片至芯片互连而短接在一起，以减少全局时钟信号相对于各种芯片位置的偏移。

    Circuit technique to electrically characterize block mask shifts
    18.
    发明授权
    Circuit technique to electrically characterize block mask shifts 有权
    电路技术，用于表征块掩模移位

    公开(公告)号：US08969104B2

    公开(公告)日：2015-03-03

    申请号：US13488532

    申请日：2012-06-05

    申请人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

    发明人： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

    IPC分类号： H01L23/34

    CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L27/0203 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

    摘要翻译： 物理测试集成电路具有对应于集成电路设计的多个重复电路部分。 这些部分中的第一部分被制造成具有标称块掩模位置，并且附加的部分被有意地用块掩模位置与标称块掩模位置的预定逐渐增加的偏移来制造。 对于每个部分，确定第一场效应晶体管和第二场效应晶体管之间的阈值电压差。 块掩模位置的预定逐渐增加的偏移在从第一场效应晶体管到第二场效应晶体管的方向上。 在与零差异的阈值电压的差的变化相对应的逐行增加偏移的值处确定块掩模覆盖公差。 还公开了用于片上监视的方法和相应的电路。

    AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
    19.
    发明授权
    AC supply noise reduction in a 3D stack with voltage sensing and clock shifting 有权
    在具有电压感测和时钟偏移的3D堆叠中的交流电源降噪

    公开(公告)号：US08587357B2

    公开(公告)日：2013-11-19

    申请号：US13217406

    申请日：2011-08-25

    申请人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    发明人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    IPC分类号： H03K5/00 ,  H03K3/00

    CPC分类号： G06F1/10 ,  G06F1/26 ,  H01L25/0657 ,  H01L2224/16145

    摘要： There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

    摘要翻译： 提供了一种具有两层或多层的3D芯片堆叠的交流电源降噪器。 每个层具有多个配电电路中的相应一个和布置在其上的多个时钟分配电路中的相应一个。 交流电源降噪器包括多个电压下降传感器和多个偏斜调整器。 多个电压下降传感器用于检测多个配电电路中的交流电源噪声。 一个或多个电压下降传感器分别布置在至少一些层上。 多个偏斜调整器用于响应于交流电源噪声的量来延迟由多个时钟分配电路提供的一个或多个时钟信号。 每个偏斜调节器分别布置在至少一些层上。