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20 条记录 (耗时 0.027 秒)

    3D chip stack skew reduction with resonant clock and inductive coupling
    3.
    发明授权
    3D chip stack skew reduction with resonant clock and inductive coupling 有权
    具有谐振时钟和电感耦合的3D芯片堆栈倾斜减少

    公开(公告)号：US08576000B2

    公开(公告)日：2013-11-05

    申请号：US13217349

    申请日：2011-08-25

    申请人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    发明人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    IPC分类号： H01L25/00

    CPC分类号： H03L7/00 ,  G06F1/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

    摘要翻译： 提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。 时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。 多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。 谐振电路包括至少一个电容器和至少一个电感器。

    AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
    5.
    发明授权
    AC supply noise reduction in a 3D stack with voltage sensing and clock shifting 有权
    在具有电压感测和时钟偏移的3D堆叠中的交流电源降噪

    公开(公告)号：US08587357B2

    公开(公告)日：2013-11-19

    申请号：US13217406

    申请日：2011-08-25

    申请人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    发明人： Jae-Joon Kim ,  Yu-Shiang Lin ,  Liang-Teck Pang ,  Joel A. Silberman

    IPC分类号： H03K5/00 ,  H03K3/00

    CPC分类号： G06F1/10 ,  G06F1/26 ,  H01L25/0657 ,  H01L2224/16145

    摘要： There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

    摘要翻译： 提供了一种具有两层或多层的3D芯片堆叠的交流电源降噪器。 每个层具有多个配电电路中的相应一个和布置在其上的多个时钟分配电路中的相应一个。 交流电源降噪器包括多个电压下降传感器和多个偏斜调整器。 多个电压下降传感器用于检测多个配电电路中的交流电源噪声。 一个或多个电压下降传感器分别布置在至少一些层上。 多个偏斜调整器用于响应于交流电源噪声的量来延迟由多个时钟分配电路提供的一个或多个时钟信号。 每个偏斜调节器分别布置在至少一些层上。

    3D integrated circuit stack-wide synchronization circuit
    6.
    发明授权
    3D integrated circuit stack-wide synchronization circuit 有权

    公开(公告)号：US08476953B2

    公开(公告)日：2013-07-02

    申请号：US13217767

    申请日：2011-08-25

    申请人： Joel A. Silberman ,  Matthew R. Wordeman

    发明人： Joel A. Silberman ,  Matthew R. Wordeman

    IPC分类号： G06F1/04 ,  H03K3/00

    CPC分类号： H03L7/00 ,  G06F1/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

    3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT
    8.
    发明申请
    3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT 有权

    公开(公告)号：US20130049825A1

    公开(公告)日：2013-02-28

    申请号：US13217767

    申请日：2011-08-25

    申请人： Joel A. Silberman ,  Matthew R. Wordeman

    发明人： Joel A. Silberman ,  Matthew R. Wordeman

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00 ,  G06F1/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

    Dependency Matrix with Reduced Area and Power Consumption
    9.
    发明申请
    Dependency Matrix with Reduced Area and Power Consumption 失效
    具有减小面积和功耗的依赖矩阵

    公开(公告)号：US20100257336A1

    公开(公告)日：2010-10-07

    申请号：US12417768

    申请日：2009-04-03

    申请人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    发明人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    IPC分类号： G06F9/44 ,  G06F15/00 ,  G06F9/30

    CPC分类号： G06F9/3838

    摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

    摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。