公开(公告)号：US11869879B2

公开(公告)日：2024-01-09

申请号：US17965530

申请日：2022-10-13

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Do Hyung Kim ,  Jung Soo Park ,  Seung Chul Han

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/544

CPC分类号： H01L25/0657 ,  H01L21/4867 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2224/131 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1058 ,  H01L2924/1531 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/83102 ,  H01L2924/00014

摘要： A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

公开(公告)号：US20190198451A1

公开(公告)日：2019-06-27

申请号：US16225374

申请日：2018-12-19

申请人： Skyworks Solutions, Inc.

发明人： Matthew Sean Read ,  Hoang Mong Nguyen ,  Anthony James LoBianco ,  Howard E. Chen ,  Dinhphuoc Vu Hoang

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/66

CPC分类号： H01L23/552 ,  H01L21/563 ,  H01L21/565 ,  H01L23/66 ,  H01L24/27 ,  H01L24/32 ,  H01L24/97 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29139 ,  H01L2224/29194 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19107 ,  H01Q1/526 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s).

公开(公告)号：US20180090339A1

公开(公告)日：2018-03-29

申请号：US15828334

申请日：2017-11-30

申请人： Subtron Technology Co., Ltd.

发明人： Chin-Sheng Wang ,  Shih-Hao Sun

IPC分类号： H01L21/56 ,  H01L23/13 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC分类号： H01L21/56 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2221/68359 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/1531 ,  Y10T29/4913 ,  H01L2924/00014 ,  H01L2924/00

摘要： A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.

公开(公告)号：US20180068985A1

公开(公告)日：2018-03-08

申请号：US15809429

申请日：2017-11-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Hsiang Chiu ,  Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Sheng-Feng Weng ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L21/683 ,  H01L23/00 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/1531 ,  H01L2924/18162 ,  H01L2924/00

摘要： A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.

公开(公告)号：US09773747B2

公开(公告)日：2017-09-26

申请号：US13868449

申请日：2013-04-23

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Kazuhiro Kainuma ,  Toshimitsu Omiya ,  Koichi Hara ,  Junji Sato

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18 ,  H01L23/31 ,  H01L23/13 ,  H05K3/46

CPC分类号： H01L24/18 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/171 ,  H05K1/188 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10636 ,  H05K2203/1461 ,  Y02P70/611 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

摘要： A wiring substrate includes a core substrate. The core substrate includes a first surface, a second surface, and an opening extending through the core substrate between the first and second surfaces. A first conductive film is formed on the first surface and covers the opening. A second conductive film is formed on the second surface. The second conductive film covers the opening. An electronic component is arranged in the opening and connected to the first conductive film. An insulator fills the opening. A first wiring portion includes alternately stacked insulative layers and wiring layers and covers the first surface of the core substrate and the first conductive film. A second wiring portion includes alternately stacked insulative layers and wiring layers, and covers the second surface of the core substrate and the second conductive film.

公开(公告)号：US09699908B2

公开(公告)日：2017-07-04

申请号：US14627194

申请日：2015-02-20

申请人： Murata Manufacturing Co., Ltd.

发明人： Takahiro Baba ,  Yuki Wakabayashi

IPC分类号： H05K1/18 ,  H01L23/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC分类号： H05K1/183 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/19105 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/181 ,  H05K1/186 ,  H05K3/4617 ,  H05K2201/0141 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2203/0278 ,  H05K2203/063 ,  H01L2924/00

摘要： A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.

公开(公告)号：US09691710B1

公开(公告)日：2017-06-27

申请号：US14959768

申请日：2015-12-04

申请人： CYNTEC CO., LTD.

发明人： Joseph D. S. Deng ,  Chia-Hsien Shen ,  Shu-Wei Chang ,  Kuan-Chih Huang

IPC分类号： H01L21/00 ,  H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/81

摘要： A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device (SMD) component, a mold compound, a printed circuit board (PCB) antenna and a conductive solder. The RF pad is used to receive or transmit an RF signal on the top side of the substrate. The SMD component is mounted on the RF pad. The mold compound on the top side of the substrate covers the semiconductor component and the SMD component. The PCB antenna is located on the mold compound. Wherein, the conductive solder and the SMD component are stacked between the RF pad and a feeding structure of the PCB antenna.

公开(公告)号：US20170062294A1

公开(公告)日：2017-03-02

申请号：US15309163

申请日：2015-06-23

申请人： zGlue, Inc.

发明人： Jawad Nasrullah ,  Ming Zhang

IPC分类号： H01L21/66 ,  G06F17/50 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L22/34 ,  G01R31/2851 ,  G06F17/5077 ,  H01L22/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/1713 ,  H01L2224/17177 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81908 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

摘要翻译： 根据这里的一些示例的系统包括可以包括用于将管芯附接到其上的多个附接槽的基座芯片。 一个或多个附接槽可以是可编程的附接槽。 基本芯片还可以包括用于互连连接到基座芯片的管芯的电路。 例如，基座芯片可以包括多个横杆开关，每个交叉开关与多个附接槽中的相应的开关相关联。 基本芯片还可以包括配置块，其适于在一个或多个管芯附接到基座芯片时接收和发送用于确定一个或多个连接槽的电连接的信号线的测试信号，并且还适于接收配置 交叉开关的编程信号（包括电源和接地）通道的数据。

公开(公告)号：US09543242B1

公开(公告)日：2017-01-10

申请号：US14823689

申请日：2015-08-11

申请人： Amkor Technology, Inc.

发明人： Michael Kelly ,  David Hiner ,  Ronald Huemoeller ,  Roger St. Amand

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/07

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/071 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

摘要： A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

摘要翻译： 半导体器件结构和制造半导体器件的方法。 作为非限制性示例，本公开的各个方面提供了包括薄细间距再分布结构的各种半导体封装结构及其制造方法。

公开(公告)号：US20160358892A1

公开(公告)日：2016-12-08

申请号：US15172097

申请日：2016-06-02

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Haksun LEE ,  KWANG-SEONG CHOI ,  Hyun-cheol BAE ,  Yong Sung EOM

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Provided is a method for manufacturing a semiconductor package, which includes providing a first substrate, providing, over the first substrate, a second substrate including an active region in which a semiconductor element is disposed and a periphery region surrounding the active region, providing an adhesive membrane between the first and second substrates, and mounting the second substrate on the first substrate, wherein the mounting of the second substrate includes aligning the second substrate on the first substrate by using an alignment member protruding from the periphery region of the second substrate.

摘要翻译： 提供一种制造半导体封装的方法，其包括提供第一衬底，在第一衬底上提供包括其中设置有半导体元件的有源区域和包围有源区域的周边区域的第二衬底，提供粘合剂 膜，并且将第二基板安装在第一基板上，其中第二基板的安装包括通过使用从第二基板的周边区域突出的对准构件来将第二基板对准在第一基板上。