公开(公告)号：US11881476B2

公开(公告)日：2024-01-23

申请号：US17664841

申请日：2022-05-24

Applicant: Semtech Corporation

Inventor： Changjun Huang ,  Jonathan Clark

IPC: H01L25/00 ,  H01L23/60 ,  H01L23/495 ,  H01L27/02 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/49575 ,  H01L23/60 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L21/304 ,  H01L21/561 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L27/0255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08148 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/8082 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/8182 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1033 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/11901 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

公开(公告)号：US20190198315A1

公开(公告)日：2019-06-27

申请号：US16265709

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Hoyoung KIM ,  Hyo-Sun LEE ,  Soojin KIM ,  Keonyoung KIM ,  JINHYE BAE ,  HOON HAN ,  Tae Soo KWON ,  Jung Hun LIM

IPC: H01L21/02 ,  C11D7/08 ,  C11D7/26 ,  C11D7/32 ,  H01L21/683 ,  H01L23/00 ,  C11D11/00

CPC classification number: H01L21/02068 ,  C11D7/08 ,  C11D7/261 ,  C11D7/264 ,  C11D7/266 ,  C11D7/3209 ,  C11D7/3218 ,  C11D11/0047 ,  H01L21/02057 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/11 ,  H01L2224/03

Abstract: Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less thaadminn 90 wt %, quaternary ammonium salt, and primary amine.

公开(公告)号：US20190164881A1

公开(公告)日：2019-05-30

申请号：US16264195

申请日：2019-01-31

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Dustin P. WOOD ,  Debendra MALLIK

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/522 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L23/50 ,  G06F17/5068 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US20180329140A1

公开(公告)日：2018-11-15

申请号：US16029365

申请日：2018-07-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Charles Baudot

IPC: G02B6/12 ,  H01L25/04 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H02S40/44

CPC classification number: G02B6/12004 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L25/043 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H02S40/44 ,  H01L2224/13099

Abstract: A method for making an electro-optic device includes forming a first photonic device having a first material in a first photonic layer over a substrate layer. A second photonic layer with a second photonic device is formed over the first photonic layer and includes a second material different than the first material. A dielectric layer is formed over the second photonic layer. A first electrically conductive via extending through the dielectric layer and the second photonic layer is formed so as to couple to the first photonic device. A second electrically conductive via extending through the dielectric layer and coupling to the second photonic device is formed. A third electrically conductive via extending through the dielectric layer, the second photonic layer, and the first photonic layer is formed so as to couple to the substrate layer.

公开(公告)号：US20180145011A1

公开(公告)日：2018-05-24

申请号：US15801935

申请日：2017-11-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng LIN

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05563 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08147 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.

公开(公告)号：US09978720B2

公开(公告)日：2018-05-22

申请号：US15201624

申请日：2016-07-05

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Gottfried Beer ,  Juergen Hoegerl

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/522 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.

公开(公告)号：US09929050B2

公开(公告)日：2018-03-27

申请号：US13943245

申请日：2013-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/06

CPC classification number: H01L21/76898 ,  H01L21/76849 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

公开(公告)号：US20180068952A1

公开(公告)日：2018-03-08

申请号：US15799624

申请日：2017-10-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Moon Hee YI ,  Joo Hwan JUNG ,  Yul Kyo CHUNG

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14177 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

公开(公告)号：US09853003B1

公开(公告)日：2017-12-26

申请号：US15480573

申请日：2017-04-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Ja Han ,  Seong Hee Choi ,  Han Kim ,  Moon Il Kim ,  Dae Hyun Park

IPC: H01L23/00 ,  H01L23/48 ,  H01L29/40 ,  H01L23/64 ,  H01L23/31

CPC classification number: H01L23/645 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24195 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/37001

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

公开(公告)号：US09847272B2

公开(公告)日：2017-12-19

申请号：US14138593

申请日：2013-12-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Juan Boon Tan ,  Wei Liu ,  Kheng Chok Tee ,  Kam Chew Leong

IPC: F25B21/00 ,  F25B21/02 ,  F25B21/04 ,  H01L35/00 ,  H01L35/04 ,  H01L23/38 ,  H01L23/48 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/38 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures are disclosed. In one exemplary embodiment, a three-dimensional integrated circuit structure includes a plurality of integrated circuit chips stacked one on top of another to form a three-dimensional chip stack, a thermoelectric cooling daisy chain comprising a plurality of vias electrically connected in series with one another formed surrounding the three-dimensional chip stack, a thermoelectric cooling plate electrically connected in series with the thermoelectric cooling daisy chain, and a heat sink physically connected with the thermoelectric cooling plate.