公开(公告)号：US07254806B1

公开(公告)日：2007-08-07

申请号：US09434394

申请日：1999-11-04

申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

IPC分类号： G06F9/45 ,  G06F15/00

CPC分类号： G06F9/45558 ,  G06F9/45554 ,  G06F2009/45583

摘要： A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.

摘要翻译： 计算机二进制翻译器将程序的二进制表示的至少一段从第一指令集架构转换为第二指令集体系结构。 翻译中的副作用序列与原始的副作用序列不同。 该翻译区分被认为被定向到良好行为的存储器的存储器负载，这些存储器负载相信被定向到不良行为的存储器件。 指令执行电路识别具有通过转换重新排序的副作用的存储器引用，已经将翻译时间相信的存储器引用指向良好的存储器，但是在执行时，发现该引用不能被保证 表现良好。 指令执行电路识别副作用顺序的差异是否可能对程序的执行产生重大影响。 建立回滚程序状态，并恢复原始代码的执行。

公开(公告)号：US06941545B1

公开(公告)日：2005-09-06

申请号：US09322443

申请日：1999-05-28

申请人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

发明人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

IPC分类号： G06F9/455 ,  G06F9/44

CPC分类号： G06F9/45554 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45583

摘要： A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

摘要翻译： 一台电脑。 指令流水线和存储器访问单元在计算机的存储器的逻辑地址空间中执行指令。 地址转换电路将由程序生成的地址参考从程序的逻辑地址空间转换为计算机的物理地址空间。 简档电路与指令流水线协作地互连，并且被配置为在没有编译器帮助执行分析的情况下检测在指令流水线中发生的可概要事件的发生，并且与存储器访问单元协作地互连以记录描述参考的物理存储器地址的简档信息 程序的执行间隔。

公开(公告)号：US06978462B1

公开(公告)日：2005-12-20

申请号：US09332263

申请日：1999-06-11

申请人： Michael C. Adler ,  John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell

发明人： Michael C. Adler ,  John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell

IPC分类号： G06F3/00

CPC分类号： G06F11/348 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3851

摘要： A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

摘要翻译： 具有指令流水线和简档电路的计算机。 简档电路检测和记录，无需编译器协助执行分析，描述描述在指令流水线中发生的事件序列的简档信息。 该序列包括在分析执行间隔期间发生的每个事件，其与要分析的事件的时间无关的选择标准相匹配。 记录继续，直到达到预定的停止条件。 配置文件电路在非分析执行间隔之后检测预定条件的发生，然后开始分析执行间隔。

公开(公告)号：US07137110B1

公开(公告)日：2006-11-14

申请号：US09330852

申请日：1999-06-11

申请人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee

发明人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee

IPC分类号： G06F9/45

CPC分类号： G06F9/45554 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45583

摘要： Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a profiled execution interval, and records profile information describing every profileable event during that interval. The profiled information includes at least all divergence of execution from sequential execution and processor mode changes not inferable from instruction opcode. The recorded profile information is efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency, and indicates contiguous ranges of sequential instructions executed during a profiled interval by low and high boundaries of the contiguous ranges, indicating the high boundary by the address of the last byte. The profile information identifies each distinct physical page of instruction text executed during the interval.

摘要翻译： 分析程序的执行。 程序以模式相关的指令集编码。 在配置文件静态执行间隔期间，配置文件电路不记录配置文件信息。 在检测到触发事件之后，简档电路开始分析执行间隔，并且记录在该间隔期间描述每个可描述事件的简档信息。 分析信息至少包括从顺序执行执行的所有分歧和处理器模式改变，不能从指令操作码推断出。 记录的配置文件信息被有效地定制以用足够的处理器模式信息来注释分布式二进制代码以解决模式依赖性，并且指示在间隔间隔期间通过连续范围的低和高边界执行的连续指令的连续范围，指示高边界 通过最后一个字节的地址。 简档信息标识在间隔期间执行的指令文本的每个不同物理页。

公开(公告)号：US07111290B1

公开(公告)日：2006-09-19

申请号：US09425401

申请日：1999-10-22

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee

IPC分类号： G06F9/45

CPC分类号： G06F9/45533

摘要： A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled for profiled execution. The program is coded in an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in the binary representation of the instruction. The recorded profile information describes at least all events occurring during the profiled execution interval of the two classes: (1) a divergence of execution from sequential execution; and (2) a processor mode change that is not inferable from the opcode of the instruction that induces the processor mode change taken together with a processor mode before the mode change instruction. The profile information further identifies each distinct physical page of instruction text executed during the execution interval.

摘要翻译： 公开了一种配置用于执行该方法的电路的方法和计算机。 在计算机上执行程序的轮廓间隔期间，描述描述执行的简档信息，而没有编译用于轮廓执行的程序。 程序被编码在指令集中，其中指令的解释取决于在指令的二进制表示中未表达的处理器模式。 记录的简档信息至少描述了在两个类的分析执行间隔期间发生的所有事件：（1）执行从顺序执行的分歧; 和（2）在模式改变指令之前，与处理器模式改变一起引导处理器模式改变的处理器模式改变，其不能从引导处理器模式改变的指令的操作码推断。 简档信息进一步标识在执行间隔期间执行的指令文本的每个不同物理页。

公开(公告)号：US5765206A

公开(公告)日：1998-06-09

申请号：US608571

申请日：1996-02-28

申请人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

发明人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/318 ,  G06F9/34 ,  G06F12/10

CPC分类号： G06F9/45537 ,  G06F12/1036 ,  G06F12/109 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/34

摘要： A processor processes a segmented to linear virtual address conversion instruction to convert segmented virtual addresses in a segmented virtual address space to a linear virtual address in a linear virtual address space. The segmented virtual address space comprises a plurality of segments each identified by a segment identifier, each segment comprising at least one page identified by a page identifier. The linear virtual address space includes a plurality of pages each identified by a page identifier. In processing the segmented to linear virtual address conversion instruction, the processor uses a plurality of segmented to linear virtual address conversion descriptors, each associated with a page in the segmented virtual address space, each segmented to linear virtual address conversion descriptor identifying the page identifier of one of the pages in the linear virtual address space. The segmented to linear virtual address conversion instruction includes a segmented virtual address identifier in the segmented virtual address space. In processing the segmented to linear virtual address conversion instruction, the processor uses the segmented virtual address identifier in the segmented to linear virtual address conversion instruction to select one of the segmented to linear virtual address conversion descriptors. After selecting a segmented to linear virtual address conversion descriptor, the processor uses the page identifier of the linear virtual address space from the selected segmented to linear virtual address conversion descriptor and the segmented virtual address identifier in the segmented to linear virtual address conversion instruction in generating a virtual address in the linear virtual address space.

摘要翻译： 处理器处理分段到线性虚拟地址转换指令，以将分段虚拟地址空间中的分段虚拟地址转换为线性虚拟地址空间中的线性虚拟地址。 分割的虚拟地址空间包括多个片段，每个片段由片段标识符标识，每个片段包括由页面标识符标识的至少一个页面。 线性虚拟地址空间包括由页面标识符标识的多个页面。 在处理分段到线性虚拟地址转换指令时，处理器使用多个分段到线性的虚拟地址转换描述符，每个分割到线性虚拟地址转换描述符与分段的虚拟地址空间中的一个页面相关联，每个划分为线性虚拟地址转换描述符， 线性虚拟地址空间中的一个页面。 分段到线性虚拟地址转换指令包括分段虚拟地址空间中的分段虚拟地址标识符。 在处理分段到线性虚拟地址转换指令时，处理器使用分段到线性虚拟地址转换指令中的分段虚拟地址标识符来选择分段到线性虚拟地址转换描述符之一。 在选择分段到线性虚拟地址转换描述符之后，处理器使用从所选择的分段到线性虚拟地址转换描述符的线性虚拟地址空间的页面标识符和分段到线性虚拟地址转换指令中的分段虚拟地址标识符，以生成 线性虚拟地址空间中的虚拟地址。

公开(公告)号：US6064815A

公开(公告)日：2000-05-16

申请号：US207476

申请日：1998-12-08

申请人： Paul H. Hohensee ,  David L. Reese

发明人： Paul H. Hohensee ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3861

摘要： A system for avoiding exceptional conditions during execution of a program comprises an execution enviornment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

摘要翻译： 用于在执行程序期间避免异常情况的系统包括用于执行程序的执行环境和修复代码生成子系统。 该程序包括包括一系列指令的指令流，并且执行环境包括例外条件检测器，用于与指令流中的每个指令的执行相关联地检测至少一种预定类型的异常条件。 固定代码生成子系统响应于执行环境检测与指令流中的指令的执行相关联的预定类型的异常情况，用于产生修正代码，该修正代码在被处理时将避免例外情况 并且将指令流中的修正代码替换为检测到至少一个异常条件的指令流中的指令。 结果，如果引起异常的指令处于循环等中，则代替正在处理的指令，将处理修正代码，这将避免异常情况。

公开(公告)号：US5907708A

公开(公告)日：1999-05-25

申请号：US657112

申请日：1996-06-03

申请人： Paul H. Hohensee ,  David L. Reese

发明人： Paul H. Hohensee ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3861

摘要： A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

摘要翻译： 用于在执行程序期间避免异常情况的系统包括用于执行程序的执行环境和修补代码生成子系统。 该程序包括包括一系列指令的指令流，并且执行环境包括例外条件检测器，用于与指令流中的每个指令的执行相关联地检测至少一种预定类型的异常条件。 固定代码生成子系统响应于执行环境检测与指令流中的指令的执行相关联的预定类型的异常情况，用于产生修正代码，该修正代码在被处理时将避免例外情况 并且将指令流中的修正代码替换为检测到至少一个异常条件的指令流中的指令。 结果，如果引起异常的指令处于循环等中，则代替正在处理的指令，将处理修正代码，这将避免异常情况。

公开(公告)号：US08683483B2

公开(公告)日：2014-03-25

申请号：US12054491

申请日：2008-03-25

申请人： Paul H. Hohensee

发明人： Paul H. Hohensee

IPC分类号： G06F9/46

CPC分类号： G06F9/5088 ,  G06F9/3851 ,  G06F2209/5022

摘要： Load-balancing threads among a plurality of processing units. The method may include a first processing unit executing a plurality of software threads using a respective plurality of hardware strands. The plurality of hardware strands may share at least one hardware resource within the first processing unit. The method may further include monitoring the at least one hardware resource, wherein, for each respective hardware strand. Monitoring may include, for each respective hardware resource of the at least one hardware resource: maintaining information regarding the respective hardware strand requesting to use the respective hardware resource but failing to do so because the respective hardware resource is in use, comparing the information to a threshold, and generating an interrupt if the information exceeds the threshold. One or more load-balancing operations may be performed in response to the interrupt.

摘要翻译： 在多个处理单元之间负载平衡线程。 该方法可以包括使用相应的多个硬件线执行多个软件线程的第一处理单元。 多个硬件链可以在第一处理单元内共享至少一个硬件资源。 该方法还可以包括监视至少一个硬件资源，其中，对于每个相应的硬件链。 对于至少一个硬件资源的每个相应的硬件资源，监视可以包括：维护关于相应的硬件链的信息，请求使用相应的硬件资源，但由于相应的硬件资源正在使用而不能这样做，将该信息与 阈值，如果信息超过阈值，则产生中断。 可以响应于中断来执行一个或多个负载平衡操作。

公开(公告)号：US5778211A

公开(公告)日：1998-07-07

申请号：US602158

申请日：1996-02-15

申请人： Paul H. Hohensee ,  David Dice

发明人： Paul H. Hohensee ,  David Dice

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/00 ,  G06F9/46

CPC分类号： G06F9/3865 ,  G06F9/45554

摘要： A digital computer system comprises a precise exception handling processor and a control subsystem. The precise exception handling processor performs processing operations under control of instructions. The precise exception handling processor is constructed in accordance with a precise exception handling model, in which, if an exception condition is detected in connection with an instruction, the exception condition is processed in connection with the instruction. The precise exception handling processor further includes a pending exception indicator having a pending exception indication state and a no pending exception indication state. The control subsystem provides a series of instructions to the precise exception handling processor to facilitate emulation of at least one emulated program instruction. The emulated program instruction is constructed to be processed by a delayed exception handling processor which is constructed in accordance with a delayed exception handling model, in which if an exception is detected during processing of an instruction, the exception condition is processed in connection with a subsequent instruction. The series of instructions provided by the control subsystem in emulation of the emulated program instruction controls the precise exception handling processor to (i) determine whether the pending exception indicator is in the pending exception indication state and, if so, to invoke a routine to process the pending exception and condition the pending exception indicator to the no pending exception indication state (ii) perform processing operations in accordance with the emulated processing instruction; and (iii) if an exception condition is detected during the processing operations, to invoke an exception handler in accordance with the processor's precise exception handling model to condition the pending exception indicator to the pending exception indication state, so that the exception condition will be processed during processing operations for a subsequent emulated program instruction.