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11.发明授权VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers 失效VME总线将系统广播修改器传输到多个设备，并且多个设备同时接收数据到修改器的数据，而无需确认修改器
公开(公告)号：US5590372A
公开(公告)日：1996-12-31
申请号：US913270
申请日：1992-07-14
CPC分类号： G06F13/4213
摘要： A method for synchronous broadcasting of multiple bytes over a VME bus broadcasts multiple bytes of data across the VME bus using hardware which interfaces between the bus and attached devices. An VME address modifier code is used to identify the type of broadcast and is sent by a master device, without requiring any response from the slave devices. In a first type of broadcast an address location is transmitted over the address bus and a data message is transmitted over the data bus. In a second type of broadcast data messages are transmitted over both the data and the address buses. Multiple broadcast cycles are used to transmit the desired amount of data. An address strobe qualifies the address and data buses for a message broadcast cycle and is used by the receiving slave to clock in the message.
摘要翻译： 一种用于通过VME总线同步广播多个字节的方法通过使用总线和附加设备之间的接口的硬件在VME总线上广播多个字节的数据。 VME地址修改码用于标识广播的类型并由主设备发送，而不需要来自从设备的任何响应。 在第一类广播中，通过地址总线传送地址位置，并通过数据总线发送数据消息。 在第二种类型的广播数据消息通过数据和地址总线发送。 使用多个广播周期来传送期望的数据量。 地址选通符限定了消息广播周期的地址和数据总线，并且被接收从机用于消息中的时钟。
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12.发明授权Apparatus and method for decreasing the latency between instruction cache and a pipeline processor 失效用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法公开(公告)号：US07711930B2
公开(公告)日：2010-05-04
申请号：US11868557
申请日：2007-10-08
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。
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公开(公告)号：US07685373B2
公开(公告)日：2010-03-23
申请号：US11970599
申请日：2008-01-08
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据 窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。
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14.发明授权Data transfer bus system and method serving multiple parallel asynchronous units 失效数据传输总线系统和方法服务多个并行异步单元
公开(公告)号：US5333301A
公开(公告)日：1994-07-26
申请号：US626706
申请日：1990-12-14
CPC分类号： G06F13/4226
摘要： A system and method for transferring data between a single channel unit and multiple asynchronous storage devices. One embodiment of the present invention uses read strobe signals to indicate when the storage devices are to send data over a data bus, and to initiate a validity count-down which indicates when the data on the data bus is valid. When the count-down has completed, the data on the data bus is sampled. Another embodiment further includes checking the data for array parity errors while the data is sent and received to and from the storage devices.
摘要翻译： 一种用于在单个通道单元和多个异步存储设备之间传输数据的系统和方法。 本发明的一个实施例使用读选通信号来指示存储设备何时通过数据总线发送数据，并且启动指示数据总线上的数据何时有效的有效性倒计数。 当倒计时完成时，对数据总线上的数据进行采样。 另一个实施例还包括在将数据发送到存储设备和从存储设备接收数据时，检查数据的阵列奇偶校验错误。
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15.发明授权Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector 失效使用多位年龄向量在微处理器流水线架构中避免数据依赖性危害的方法和装置公开(公告)号：US07730282B2
公开(公告)日：2010-06-01
申请号：US10916188
申请日：2004-08-11
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/3855
摘要： A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.
摘要翻译： 一种用于避免通过微处理器管道传播的指令的各种危险的方法和系统。 当流水线内存在多个读取和写入相同值的指令时，建立一个向量来区分较旧的指令。 此外，在分派指令执行之前，生成指针，该指针标识具有操作数或参数值所需的特定指令。 因此，通过监视最近的向量和指针，可以避免日期依赖危害。
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公开(公告)号：US07319578B2
公开(公告)日：2008-01-15
申请号：US11148090
申请日：2005-06-08
申请人： James N. Dieffenderfer , Praveen Karandikar , Michael B. Mitchell , Thomas P. Speier , Paul M. Steinmetz
发明人： James N. Dieffenderfer , Praveen Karandikar , Michael B. Mitchell , Thomas P. Speier , Paul M. Steinmetz
IPC分类号： H02H5/04
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.
摘要翻译： 提供了一种方法和装置，用于确定I / C芯片上对于芯片的未消耗电力的功率事件，并且其中芯片包括多个单独调节的功率消耗器。 提供了一种结构，用于监测每个电力消费者的每个电力事件的发生，以及确定来自每个电力事件的功率的耗散，以及响应于未消耗电力的量来控制芯片使用的电力。
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公开(公告)号：US06970962B2
公开(公告)日：2005-11-29
申请号：US10440778
申请日：2003-05-19
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
CPC分类号： G06F12/0831 , G06F13/4217 , G06F2213/0038 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.
摘要翻译： 一种用于在计算机系统内互连设备的流水线总线接口宏的方法和系统。 该系统和方法利用流水线深度信号，其指示可以由发送设备发送并由接收设备在接收设备确认传送请求之前由接收设备发送的离散传送请求的数量N。 可以动态地修改流水线深度信号，使得接收设备在已经做出一个或多个未确认的请求时减小或增加流水线深度。 动态修改可以响应许多因素而发生，例如系统功耗的瞬时降低，总线接口性能指示器，接收设备性能指标或系统性能指标。
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18.发明授权公开(公告)号：US07395372B2
公开(公告)日：2008-07-01
申请号：US10714105
申请日：2003-11-14
申请人： Anthony Correale, Jr. , James N. Dieffenderfer , Robert L. Goldiez , Thomas P. Speier , William R. Reohr
发明人： Anthony Correale, Jr. , James N. Dieffenderfer , Robert L. Goldiez , Thomas P. Speier , William R. Reohr
CPC分类号： G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.
摘要翻译： 一种用于访问具有至少两种在相同地址处存储数据的方式的数据高速缓存的系统和方法。 第一和第二标签存储器存储识别以每种方式存储的数据的第一和第二组标签。 翻译装置从系统地址确定识别方式之一的标签。 第一个比较器将地址中的标签与存储在第一标签存储器中的标签进行比较。 第二比较器将地址中的标签与存储在第二标签存储器中的标签进行比较。 响应于访问模式信号，时钟信号将时钟信号提供给一种或两种方式。 可以对系统进行操作，使得关联数据高速缓存的两种方式都以高速访问模式被计时，或者它可以将时钟信号仅以来自第一和第二比较器的输出的功率中的一种方式应用于时钟信号 高效的运行模式。
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19.发明授权Method for software controllable dynamically lockable cache line replacement system 有权软件可控动态锁定缓存线替换系统的方法公开(公告)号：US07321954B2
公开(公告)日：2008-01-22
申请号：US10915982
申请日：2004-08-11
CPC分类号： G06F12/126 , G06F12/125
摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
摘要翻译： 用于跟踪关联高速缓存行的访问的LRU数组和方法。 缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。 高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。 第二组数据识别一条路线是否不被替换。 对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为 锁定 对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。
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20.发明授权Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor 失效用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法公开(公告)号：US07281120B2
公开(公告)日：2007-10-09
申请号：US10810235
申请日：2004-03-26
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。
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