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公开(公告)号：US20130009215A1
公开(公告)日：2013-01-10
申请号：US13618738
申请日：2012-09-14
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/861 , H01L29/6609 , H01L29/66356 , H01L29/7391
摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
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公开(公告)号：US07888775B2
公开(公告)日：2011-02-15
申请号：US11862964
申请日：2007-09-27
IPC分类号： H01L27/08
CPC分类号： H01L29/861 , H01L29/6609 , H01L29/66356 , H01L29/7391
摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
摘要翻译： 一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。 一些实施例包括引起垂直和横向二极管活动的装置。 一些实施例包括用于翅片半导体装置的门控垂直二极管。 工艺实施例包括形成垂直二极管装置。
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公开(公告)号：US20100193867A1
公开(公告)日：2010-08-05
申请号：US12364804
申请日：2009-02-03
申请人： Jiang Yan , Henning Haffiner , Frank Huebinger , SunOo Kim , Richard Lindsay , Klaus Schruefer
发明人： Jiang Yan , Henning Haffiner , Frank Huebinger , SunOo Kim , Richard Lindsay , Klaus Schruefer
CPC分类号： H01L27/0617 , H01L21/28088 , H01L23/5256 , H01L29/0653 , H01L29/4958 , H01L29/4966 , H01L2924/0002 , H01L2924/00
摘要： A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.
摘要翻译： 优选实施例包括制造熔丝元件的方法，该方法包括在半导体结构上形成多晶硅层，用碳或氮掺杂多晶硅层，在多晶硅层上沉积金属; 以及退火所述金属和多晶硅层以在所述多晶硅层的上部形成硅化物。
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公开(公告)号：US08310027B2
公开(公告)日：2012-11-13
申请号：US12138319
申请日：2008-06-12
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L21/8228 , H01L21/823814 , H01L21/823821 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L27/092 , H01L29/66265 , H01L29/74 , H01L29/785
摘要： Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.
摘要翻译： 实施例涉及一种双极晶体管，其包括具有翅片结构的主体区域。 可以在身体区域的至少一部分上形成至少一个末端区域。 至少一个末端区域可以形成为外延生长区域。 实施例还涉及一种垂直集成的电子设备，其包括第一端子区域，第二端子区域和第三端子区域。 第二端子区域可以布置在第三端子区域的至少一部分上，并且第一，第二和第三端子区域中的至少两个可以形成为外延生长区域。
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公开(公告)号：US08106424B2
公开(公告)日：2012-01-31
申请号：US12860075
申请日：2010-08-20
申请人： Klaus Schruefer
发明人： Klaus Schruefer
IPC分类号： H01L31/072
CPC分类号： H01L29/802 , H01L29/78684 , H01L29/78687 , Y10S438/933 , Y10S438/936
摘要： A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
摘要翻译： 具有异质结构的场效应晶体管包括形成在载体材料上的应变单晶半导体层，其具有由作为最上层的第一半导体材料（Si）制成的弛豫单晶半导体层。 应变单晶半导体层具有可以自由地设定第二半导体材料的比例x的半导体合金（GexSi1-x）。 此外，在应变半导体层上形成栅极绝缘层和栅极层。 为了限定未掺杂的沟道区，至少在应变半导体层中，相对于栅极层横向形成漏极/源极区。 自由设定Ge比例x的可能性使得能够根据需要设定阈值电压，由此可以实现现代逻辑半导体部件。
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公开(公告)号：US08039904B2
公开(公告)日：2011-10-18
申请号：US12784526
申请日：2010-05-21
申请人： Ronald Kakoschke , Klaus Schruefer
发明人： Ronald Kakoschke , Klaus Schruefer
IPC分类号： H01L21/021
CPC分类号： H01L27/1052 , H01L21/84 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/41791 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141
摘要： A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
摘要翻译： 存储单元包括FinFET选择装置和存储元件。 在一些实施例中，存储器单元具有耦合在鳍片的表面和存储元件之间的接触元件。
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公开(公告)号：US20110095347A1
公开(公告)日：2011-04-28
申请号：US12986875
申请日：2011-01-07
CPC分类号： H01L29/861 , H01L29/6609 , H01L29/66356 , H01L29/7391
摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
摘要翻译： 一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。 一些实施例包括引起垂直和横向二极管活动的装置。 一些实施例包括用于翅片半导体装置的门控垂直二极管。 工艺实施例包括形成垂直二极管装置。
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公开(公告)号：US07804110B2
公开(公告)日：2010-09-28
申请号：US12353053
申请日：2009-01-13
申请人： Klaus Schruefer
发明人： Klaus Schruefer
IPC分类号： H01L31/072
CPC分类号： H01L29/802 , H01L29/78684 , H01L29/78687 , Y10S438/933 , Y10S438/936
摘要： A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1−x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
摘要翻译： 具有异质结构的场效应晶体管包括形成在载体材料上的应变单晶半导体层，其具有由作为最上层的第一半导体材料（Si）制成的弛豫单晶半导体层。 应变单晶半导体层具有可以自由地设定第二半导体材料的比例x的半导体合金（GexSi1-x）。 此外，在应变半导体层上形成栅极绝缘层和栅极层。 为了限定未掺杂的沟道区，至少在应变半导体层中，相对于栅极层横向形成漏极/源极区。 自由设定Ge比例x的可能性使得能够根据需要设定阈值电压，由此可以实现现代逻辑半导体部件。
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公开(公告)号：US07723786B2
公开(公告)日：2010-05-25
申请号：US11734069
申请日：2007-04-11
申请人： Ronald Kakoschke , Klaus Schruefer
发明人： Ronald Kakoschke , Klaus Schruefer
CPC分类号： H01L27/1052 , H01L21/84 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/41791 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141
摘要： A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
摘要翻译： 存储单元包括FinFET选择装置和存储元件。 在一些实施例中，存储器单元具有耦合在鳍片的表面和存储元件之间的接触元件。
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20.发明申请FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE AND ASSOCIATED PRODUCTION METHOD 有权具有结构和相关生产方法的场效应晶体管公开(公告)号：US20090121289A1
公开(公告)日：2009-05-14
申请号：US12353053
申请日：2009-01-13
申请人： Klaus Schruefer
发明人： Klaus Schruefer
IPC分类号： H01L29/68
CPC分类号： H01L29/802 , H01L29/78684 , H01L29/78687 , Y10S438/933 , Y10S438/936
摘要： A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1 -x),where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
摘要翻译： 具有异质结构的场效应晶体管包括形成在载体材料上的应变单晶半导体层，其具有由作为最上层的第一半导体材料（Si）制成的弛豫单晶半导体层。 应变单晶半导体层具有可以自由地设定第二半导体材料的比例x的半导体合金（GexSi1-x）。 此外，在应变半导体层上形成栅极绝缘层和栅极层。 为了限定未掺杂的沟道区，至少在应变半导体层中，相对于栅极层横向形成漏极/源极区。 自由设定Ge比例x的可能性使得能够根据需要设定阈值电压，由此可以实现现代逻辑半导体部件。
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