公开(公告)号：US20070046523A1

公开(公告)日：2007-03-01

申请号：US11463014

申请日：2006-08-08

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/502 ,  H03M1/66 ,  H03M3/464

摘要： A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

摘要翻译： 参考电压产生电路包括：第一电容器; 第二电容器; 参考电压采样电容器; 用于交替地将第二电容器耦合到预定电压以允许第二电容器对预定电压进行采样的第一开关; 用于将第二电容器交替地耦合到第一电容器的第二开关，以允许第二电容器与第一电容器重新分配电荷，以便产生参考电压; 以及第三开关，用于将第一电容器交替地耦合到参考电压采样电容器，以允许参考电压采样电容器与第一电容器重新分配电荷，以便输出参考电压。

公开(公告)号：US07019552B2

公开(公告)日：2006-03-28

申请号：US10724779

申请日：2003-12-02

申请人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03K17/16

CPC分类号： H03F1/56

摘要： The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal. Each of the resistor units and the impedance matching resistor unit includes a plurality of resistors in symmetric configuration.

摘要翻译： 具有有源终端的线路驱动器包括：具有反相输出端子，非反相输出端子，反相输入端子和非反相输入端子的差分放大器; 耦合到所述反相输入端的第一电阻器单元; 耦合到所述非反相输出端子的阻抗匹配电阻器单元; 和电阻反馈网络，具有对称配置的多个电阻器。 电阻反馈网络还包括：耦合到阻抗匹配电阻器单元和反相输入端子的第二电阻器单元; 耦合到非反相输出端子和反相输入端子的第三电阻器单元; 耦合到所述阻抗匹配电阻器单元和所述反相输入端子的第四电阻器单元; 以及耦合到反相输出端子和反相输入端子的第五电阻器单元。 每个电阻器单元和阻抗匹配电阻器单元包括多个对称配置的电阻器。

公开(公告)号：US07456769B2

公开(公告)日：2008-11-25

申请号：US11459364

申请日：2006-07-24

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M3/00

CPC分类号： G11C27/024 ,  G11C27/026

摘要： A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

摘要翻译： 参考电压产生电路包括具有第一端和第二端的第一电容器; 具有第三端和第四端的第二电容器; 用于选择性地将预定电压耦合到第一电容器的第一端的第一开关; 第二开关，用于选择性地将第二电容器的第三端耦合到第一电容器的第一端; 用于选择性地将第一电容器的第一端耦合到参考电压电平的第三开关; 以及用于选择性地将第一电容器的第二端耦合到参考电压电平的第四开关; 其中所述第一电容器在第一级中对所述预定电压进行采样，并且在第二级中将电荷重新分配给所述第二电容器。

公开(公告)号：US07138869B2

公开(公告)日：2006-11-21

申请号：US10748667

申请日：2003-12-31

申请人： Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai ,  Wen-Chi Wang

发明人： Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai ,  Wen-Chi Wang

IPC分类号： H03G3/12

CPC分类号： H03H11/126 ,  H03H7/24

摘要： An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

摘要翻译： 具有高时间常数的放大器电路。 运算放大器包括耦合到地的非转换输入端，转换输入端和输出端。 包括至少一个级的第一电阻网络耦合在转换输入端和输出端之间。 第一电阻网络的每个级包括连接到第一节点的第一节点，第一电流路径和第二电流路径。 第一电阻网络的每个级的第一电流路径连接到下一级的第一节点，第一电阻网络的每一级的第二电流路径接地，并且第一电阻网络的第一级的第一电流路径 电阻网络连接到转换输入端。 加载单元耦合在转换输入端和输出端之间。

公开(公告)号：US20080030620A1

公开(公告)日：2008-02-07

申请号：US11878890

申请日：2007-07-27

申请人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chang-Shun Liu

发明人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chang-Shun Liu

IPC分类号： H03M1/12

CPC分类号： H04N5/14

摘要： An analog front end circuit is provided, which comprises at least one converting circuit. Each converting circuit further comprises a clamper, a low-pass filter, an input buffer and a sigma-delta analog-to-digital converter. By using the sigma-delta analog to digital converter, the invention not only increases the resolution, but reduces the order of an anti-aliasing filter, therefore reducing the size and the power consumption of the analog circuit.

摘要翻译： 提供了一种模拟前端电路，其包括至少一个转换电路。 每个转换电路还包括钳位器，低通滤波器，输入缓冲器和Σ-Δ模数转换器。 通过使用Σ-Δ模数转换器，本发明不仅提高了分辨率，而且降低了抗混叠滤波器的次序，从而减小了模拟电路的尺寸和功耗。

公开(公告)号：US20100066725A1

公开(公告)日：2010-03-18

申请号：US12562113

申请日：2009-09-17

申请人： Szu-Ping Chen ,  Jui-Yuan Tsai ,  Cheng-Jui Chen

发明人： Szu-Ping Chen ,  Jui-Yuan Tsai ,  Cheng-Jui Chen

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  H04N5/185

摘要： A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

摘要翻译： DC电平再分配方法包括以下步骤：接收多对差分信号的所有正信号和一个负信号; 将多对差分信号中指定的一对差分信号的正信号的DC电平固定为参考，以便调整所指定的一对差分信号的负信号的DC电平，以产生经调整的负信号 ; 并且将所指定的差分信号对的经调整的负信号作为参考，以便调整除指定的差分信号对之外的其它对差分信号的正信号的DC电平。 DC再分配方法可以用在显示系统中。

公开(公告)号：US20100066428A1

公开(公告)日：2010-03-18

申请号：US12561266

申请日：2009-09-17

申请人： Jui-Yuan Tsai ,  Cheng-Jui Chen

发明人： Jui-Yuan Tsai ,  Cheng-Jui Chen

IPC分类号： H03L5/00

CPC分类号： G11C27/02 ,  G06F1/22 ,  G09G3/3685 ,  G09G2310/027 ,  G11C27/024

摘要： An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.

摘要翻译： 能够共享引脚的模拟前端处理装置包括多个正极引脚，负极引脚，多个正钳位电路，负钳位电路，多个采样保持电路和多个调整电路。 正钳位电路具有固定在其相应的目标正电压的正信号。 负钳位电路具有固定在第一参考电压的负信号。 每个采样和保持电路具有正输入端和负输入端，其中两个输入端之间的电压差基本上等于在采样周期期间对应的目标正电压和第一参考电压之间的电压差，并且 两个输入端子之间的电压差等于在保持期间相应的目标负电压和第二基准电压之间的电压差。

公开(公告)号：US20080036640A1

公开(公告)日：2008-02-14

申请号：US11882717

申请日：2007-08-03

申请人： Jui-Yuan Tsai

发明人： Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： G09G5/006

摘要： An image processing device is provided which includes a pseudo differential analog front end circuit for receiving at least one image analog signal and generating at least one digital signal. The pseudo differential analog front end circuit includes at least a converting circuit, each of which includes a clamper, an input buffer and an analog-to-digital converter. All of the analog-to-digital converters receive a common comparing voltage if the number of the converting circuits is greater than one.

摘要翻译： 提供一种图像处理装置，其包括用于接收至少一个图像模拟信号并产生至少一个数字信号的伪差分模拟前端电路。 伪差分模拟前端电路至少包括一个转换电路，每个转换电路都包括一个钳位器，一个输入缓冲器和一个模拟 - 数字转换器。 如果转换电路的数量大于1，则所有模数转换器都接收公共的比较电压。

公开(公告)号：US07280115B2

公开(公告)日：2007-10-09

申请号：US10771031

申请日：2004-02-03

申请人： Chi-Feng Wang ,  Szu-Ping Chen ,  Jui-Yuan Tsai ,  Jin-Sheng Gong

发明人： Chi-Feng Wang ,  Szu-Ping Chen ,  Jui-Yuan Tsai ,  Jin-Sheng Gong

IPC分类号： G09G5/02

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/02

摘要： An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.

摘要翻译： 一种适用于AFE装置的图像信号处理方法，其根据模拟信号的第一和第二颜色分别产生数字信号的第一和第二颜色。 首先，分别根据第一和第二颜色的模拟信号产生奇偶信号的第一颜色和奇偶信号的第二颜色。 在单通道模式中，奇数或偶数信号的第一颜色用作输出的数字信号的第一颜色，奇数或偶数信号的第二颜色用作用于输出的数字信号的第二颜色。 在双通道模式中，同步地输出奇数信号的第一颜色和偶数信号的第二颜色，同时输出偶数信号的第一颜色和奇数信号的第二颜色。 奇数和偶数信号的第一颜色被组合以形成数字信号的第一颜色，并且奇数和偶数信号的第二颜色被组合以形成数字信号的第二颜色。

公开(公告)号：US20080063049A1

公开(公告)日：2008-03-13

申请号：US11898347

申请日：2007-09-11

申请人： Jui-Yuan Tsai

发明人： Jui-Yuan Tsai

IPC分类号： H04N11/02

CPC分类号： H04N5/14 ,  H04N5/16 ,  H04N5/38

摘要： A video data source system includes a video encoder and an analog back end device. The analog back end device includes a digital to analog converter and a post-stage driving unit. The video data source system adds the post-stage driving unit into the analog back end device and strengthens its driving ability by the post-stage driving unit.

摘要翻译： 视频数据源系统包括视频编码器和模拟后端设备。 模拟后端装置包括数模转换器和后级驱动单元。 视频数据源系统将后级驱动单元添加到模拟后端装置中，并且通过后级驱动单元增强其驱动能力。