公开(公告)号：US20100271106A1

公开(公告)日：2010-10-28

申请号：US12723822

申请日：2010-03-15

申请人： Jun Deguchi ,  Daisuke Miyashita

发明人： Jun Deguchi ,  Daisuke Miyashita

IPC分类号： G06G7/16

CPC分类号： H03B19/14

摘要： A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a 1/2-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

摘要翻译： 半导体集成电路包括具有第一单栅极混频器的混频器电路单元，其被配置为接收具有第一频率的第一输入信号和具有第二频率的第二输入信号作为输入;第二单门混频器，被配置为接收第一输入信号 以及从所述第二输入信号的相位反转的相位的第三输入信号作为输入;第三单门混频器，被配置为接收从所述第一输入信号和所述第二输入信号的相位反相的相位的第四输入信号， 配置为接收第三和第四输入信号作为输入的第四单门混频器; 以及1/2频分频器单元，被配置为从第一至第四单栅极混频器接收输出信号作为输入并输出期望的信号。

公开(公告)号：US08716998B2

公开(公告)日：2014-05-06

申请号：US13251343

申请日：2011-10-03

申请人： Toshimasa Namekawa ,  Daisuke Miyashita ,  Jun Deguchi

发明人： Toshimasa Namekawa ,  Daisuke Miyashita ,  Jun Deguchi

IPC分类号： H02M3/157

CPC分类号： H03K7/08 ,  H02M3/157

摘要： A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals.

摘要翻译： DC-DC转换器具有开关元件，低通滤波器，振荡器，AD转换器，误差信号发生器，计数器，比较器，选择器，其被配置为根据以下值来选择多个时钟信号中的一个： 误差信号的下侧位与比较器检测到一致的定时同步;以及切换控制器，被配置为根据由选择器选择的时钟信号来控制开关元件的接通/断开。 选择器选择多个时钟信号中的一个和通过组合包括多个时钟信号中的相邻相位的两个或更多个时钟信号而产生的新的时钟信号。

公开(公告)号：US20120064844A1

公开(公告)日：2012-03-15

申请号：US13050059

申请日：2011-03-17

申请人： Daisuke Miyashita ,  Jun Deguchi

发明人： Daisuke Miyashita ,  Jun Deguchi

IPC分类号： H04B1/40 ,  H03H11/16

CPC分类号： H03L7/16

摘要： According to one embodiment, a semiconductor integrated circuit includes a phase shifter, a plurality of phase matching detecting circuits, a output module. The phase shifter is configured to delay an input oscillation signal to generate a plurality of delay signals having phases different from each other. The plurality of phase matching detecting circuits is configured to store a second program for downloading a first program from an outside to the first area. The output module is configured to generate an output oscillation signal based on at least one of the delay signals having the phase difference determined to be within the predetermined range.

摘要翻译： 根据一个实施例，半导体集成电路包括移相器，多个相位匹配检测电路，输出模块。 移相器被配置为延迟输入振荡信号以产生具有彼此不同相位的多个延迟信号。 多个相位匹配检测电路被配置为存储用于从外部向第一区域下载第一程序的第二程序。 输出模块被配置为基于确定为在预定范围内的相位差的延迟信号中的至少一个来产生输出振荡信号。

公开(公告)号：US20120063520A1

公开(公告)日：2012-03-15

申请号：US13053396

申请日：2011-03-22

申请人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

发明人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

IPC分类号： H04L27/00 ,  H03L7/06

CPC分类号： H03L7/1803 ,  H03L2207/50 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0069

摘要： According to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals.

摘要翻译： 根据一个实施例，半导体集成器件包括数字控制振荡器，计数器，时间到数字转换器，加法器和控制信号发生器。 数字转换器的时间包括分频器，多个阻抗元件和相位差检测器。 分频器被配置为对振荡信号进行分频以产生多个分频信号。 多个阻抗元件被配置为对分频信号进行分压以产生振荡信号的多个延迟信号。 相位差检测器被配置为通过将参考信号与每个延迟信号进行比较来输出与参考信号和振荡信号之间的相位差相对应的第三数字信号。

公开(公告)号：US08135374B2

公开(公告)日：2012-03-13

申请号：US12240093

申请日：2008-09-29

申请人： Shouhei Kousai ,  Daisuke Miyashita ,  Jun Deguchi

发明人： Shouhei Kousai ,  Daisuke Miyashita ,  Jun Deguchi

IPC分类号： H04B1/26

CPC分类号： H03D7/125

摘要： A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

公开(公告)号：US20100109781A1

公开(公告)日：2010-05-06

申请号：US12560828

申请日：2009-09-16

申请人： Jun DEGUCHI ,  Daisuke Miyashita

发明人： Jun DEGUCHI ,  Daisuke Miyashita

IPC分类号： H03F3/04

CPC分类号： H03F3/45183 ,  H03F1/30 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2203/45244 ,  H03F2203/45508

摘要： A semiconductor integrated circuit device includes: an amplifier circuit which respectively has one or more input terminals and one or more output terminals; a replica circuit which has the same DC characteristics as those of the amplifier circuit; a reference voltage generation circuit which is connected to a bias terminal of the replica circuit, and which generates a predetermined reference voltage at the bias terminal; and a feedback circuit which takes a difference between the reference voltage generated at the bias terminal of the replica circuit and the voltage generated at a bias terminal of the amplifier circuit, and which performs feedback control by providing negative feedback of the difference to the bias terminal of the amplifier circuit so that the voltage generated at the bias terminal of the amplifier circuit is made equal to the reference voltage generated at the bias terminal of the replica circuit.

摘要翻译： 一种半导体集成电路器件，包括：分别具有一个或多个输入端子和一个或多个输出端子的放大器电路; 具有与放大电路相同的DC特性的复制电路; 参考电压产生电路，其连接到所述复制电路的偏置端子，并且在所述偏置端子处产生预定的参考电压; 以及反馈电路，其将复制电路的偏置端子处产生的参考电压与在放大器电路的偏置端子处产生的电压之间产生差异，并且通过向偏置端子提供差分的负反馈来执行反馈控制 使得在放大器电路的偏置端产生的电压等于在复制电路的偏置端产生的参考电压。

公开(公告)号：US08451965B2

公开(公告)日：2013-05-28

申请号：US13053396

申请日：2011-03-22

申请人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

发明人： Jun Deguchi ,  Daisuke Miyashita ,  Hiroyuki Kobayashi

IPC分类号： H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08

CPC分类号： H03L7/1803 ,  H03L2207/50 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0069

摘要： According to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals.

摘要翻译： 根据一个实施例，半导体集成器件包括数字控制振荡器，计数器，时间到数字转换器，加法器和控制信号发生器。 数字转换器的时间包括分频器，多个阻抗元件和相位差检测器。 分频器被配置为对振荡信号进行分频以产生多个分频信号。 多个阻抗元件被配置为对分频信号进行分压以产生振荡信号的多个延迟信号。 相位差检测器被配置为通过将参考信号与每个延迟信号进行比较来输出与参考信号和振荡信号之间的相位差相对应的第三数字信号。

公开(公告)号：US08362820B2

公开(公告)日：2013-01-29

申请号：US13397742

申请日：2012-02-16

申请人： Jun Deguchi ,  Daisuke Miyashita

发明人： Jun Deguchi ,  Daisuke Miyashita

IPC分类号： H04B1/40 ,  H04B1/26

CPC分类号： H03B19/14

摘要： A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

摘要翻译： 半导体集成电路包括具有第一单栅极混频器的混频器电路单元，其被配置为接收具有第一频率的第一输入信号和具有第二频率的第二输入信号作为输入;第二单门混频器，被配置为接收第一输入信号 以及从所述第二输入信号的相位反转的相位的第三输入信号作为输入;第三单门混频器，被配置为接收从所述第一输入信号和所述第二输入信号的相位反相的相位的第四输入信号， 配置为接收第三和第四输入信号作为输入的第四单门混频器; 以及1/2分频器单元，被配置为从第一至第四单个栅极混合器接收输出信号作为输入并输出期望的信号。

公开(公告)号：US08233874B2

公开(公告)日：2012-07-31

申请号：US13370101

申请日：2012-02-09

申请人： Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

发明人： Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

IPC分类号： H04B15/00

CPC分类号： H04B1/0053

摘要： A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

摘要翻译： 无线通信装置包括本地振荡器，其产生对应于多个输入RF（射频）信号的频率的多个LO（局部烧灼）信号，累加器，其累积由本地振荡器产生的多个LO信号，以产生 累积信号，混合多个RF信号的混频器和由累加器产生的累加信号并产生多个基带信号;以及第一信号处理单元，其执行关于多个基带的信号处理 由混合器产生的信号。

公开(公告)号：US20120142292A1

公开(公告)日：2012-06-07

申请号：US13370101

申请日：2012-02-09

申请人： Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

发明人： Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

IPC分类号： H04B1/04

CPC分类号： H04B1/0053

摘要： A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

摘要翻译： 无线通信装置包括本地振荡器，其产生对应于多个输入RF（射频）信号的频率的多个LO（局部烧灼）信号，累加器，其累积由本地振荡器产生的多个LO信号，以产生 累积信号，混合多个RF信号的混频器和由累加器产生的累加信号并产生多个基带信号;以及第一信号处理单元，其执行关于多个基带的信号处理 由混合器产生的信号。