公开(公告)号：US20060001178A1

公开(公告)日：2006-01-05

申请号：US10883419

申请日：2004-06-30

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

公开(公告)号：US07524754B2

公开(公告)日：2009-04-28

申请号：US11320314

申请日：2005-12-27

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

摘要翻译： 在本发明的一个实施例中，集成电路封装包括集成电路，封装基板，第一凸块，第二凸块和分流器，以提供电流分配和可靠性冗余。 第一和第二凸起在集成电路和封装衬底之间提供第一和第二电流通路。 分流器在第一凸块和第二凸块之间提供第三电流通路。

公开(公告)号：US20070069331A1

公开(公告)日：2007-03-29

申请号：US11605119

申请日：2006-11-27

申请人： Jose Maiz ,  Jun He ,  Mark Bohr

发明人： Jose Maiz ,  Jun He ,  Mark Bohr

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括通过在第一互连结构上形成至少一个通孔来形成金属熔丝结构，将所述至少一个通孔与阻挡层衬里，然后在所述至少一个通孔上形成第二互连结构。

公开(公告)号：US07208830B2

公开(公告)日：2007-04-24

申请号：US10883419

申请日：2004-06-30

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

摘要翻译： 在本发明的一个实施例中，集成电路封装包括集成电路，封装基板，第一凸块，第二凸块和分流器，以提供电流分配和可靠性冗余。 第一和第二凸起在集成电路和封装衬底之间提供第一和第二电流通路。 分流器在第一凸块和第二凸块之间提供第三电流通路。

公开(公告)号：US20060097375A1

公开(公告)日：2006-05-11

申请号：US11320314

申请日：2005-12-27

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

IPC分类号： H01L23/02

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

公开(公告)号：US20080203388A1

公开(公告)日：2008-08-28

申请号：US11712355

申请日：2007-02-28

申请人： Jun He ,  Jeff Hicks ,  Chris Litteken ,  Tom Marieb ,  Alan Lucero ,  Jose Maiz ,  Jun He ,  Jeffrey Morisson Hicks

发明人： Jun He ,  Jeff Hicks ,  Chris Litteken ,  Tom Marieb ,  Alan Lucero ,  Jose Maiz ,  Jun He ,  Jeffrey Morisson Hicks

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present.

摘要翻译： 本发明的实施例能够检测半导体器件中的边缘损伤。 为此，可以提供一个或多个连续性结构，其中每个结构包括布置在半导体器件的有源电路和金属化层的周边之间的起伏布置。 连续性结构形成与半导体器件中的多个金属化层交叉的一个或多个导电路径。 监视连续性结构的电特性的相对变化，以确定是否存在边缘损伤。

公开(公告)号：USD965692S1

公开(公告)日：2022-10-04

申请号：US29819424

申请日：2021-12-15

申请人： Jun He

设计人： Jun He

公开(公告)号：US08704336B2

公开(公告)日：2014-04-22

申请号：US11848879

申请日：2007-08-31

申请人： Jun He ,  Kevin J. Lee ,  Subhash Joshi

发明人： Jun He ,  Kevin J. Lee ,  Subhash Joshi

IPC分类号： H01L23/544

CPC分类号： H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.

摘要翻译： 通常描述从划线区域选择性地去除片上再分布互连材料。 在一个示例中，一种装置包括具有再分布层的第一半导体管芯，其包括再分布电介质和一个或多个再分布金属互连，与第一半导体管芯耦合的第二半导体管芯，第二半导体管芯具有包括再分布电介质的再分配层和一个 或更多的再分配金属互连，以及设置在第一半导体管芯和第二半导体管芯之间的划线区域，划分线区域具有大部分或基本上全部的再分布电介质或再分配金属或其合适的组合， 通过划线区划分。

公开(公告)号：US08435410B2

公开(公告)日：2013-05-07

申请号：US12922357

申请日：2009-03-30

申请人： Shahab Ahmed Shamsi ,  Congying Gu ,  Jun He

发明人： Shahab Ahmed Shamsi ,  Congying Gu ,  Jun He

IPC分类号： B01D15/08

CPC分类号： C08J9/127 ,  B01J20/261 ,  B01J20/267 ,  B01J20/28042 ,  B01J20/285 ,  B01J2220/82 ,  G01N2030/528

摘要： A method for making a surfactant-based monolithic column is provided. The method comprises providing a mixture comprising at least one surfactant monomer, at least one crosslinker, at least one initiator, and at least one porogen and polymerizing the mixture to form the surfactant-based monolithic column. The present disclosure also provides a surfactant-based monolithic column, a method for separating molecules, and a process for preparing a surfactant monomer.

摘要翻译： 提供了制备基于表面活性剂的整体柱的方法。 该方法包括提供包含至少一种表面活性剂单体，至少一种交联剂，至少一种引发剂和至少一种致孔剂的混合物，并使混合物聚合以形成基于表面活性剂的整体柱。 本公开还提供了一种基于表面活性剂的整体柱，分离分子的方法和制备表面活性剂单体的方法。

公开(公告)号：US20120007242A1

公开(公告)日：2012-01-12

申请号：US13242988

申请日：2011-09-23

申请人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

发明人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

IPC分类号： H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

摘要翻译： 制造用于微电子器件的封盖互连的方法，其包括封盖层和互连件之间的任何间隙的密封特征以及由其形成的结构。 密封特征改善了互连的封装，其基本上减少或防止导电材料从封盖互连件的电迁移和/或扩散。