利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.016 秒)

    Integrated circuit package substrate
    1.
    发明授权
    Integrated circuit package substrate 有权

    公开(公告)号：US10242942B2

    公开(公告)日：2019-03-26

    申请号：US15127708

    申请日：2014-04-25

    申请人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

    发明人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

    IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

    摘要： Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

    Chip package with degassing holes
    2.
    发明授权
    Chip package with degassing holes 失效
    芯片封装带脱气孔

    公开(公告)号：US06831233B2

    公开(公告)日：2004-12-14

    申请号：US09800703

    申请日：2001-03-07

    申请人： Dustin P. Wood

    发明人： Dustin P. Wood

    IPC分类号： H05K100

    CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

    摘要： A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

    摘要翻译： 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。

    Array capacitors with voids to enable a full-grid socket
    4.
    发明授权
    Array capacitors with voids to enable a full-grid socket 有权
    具有空隙的阵列电容器，以实现全网插座

    公开(公告)号：US07463492B2

    公开(公告)日：2008-12-09

    申请号：US11823522

    申请日：2007-06-26

    申请人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

    发明人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

    IPC分类号： H05K7/00

    CPC分类号： H01G4/242 ,  H01G2/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L2224/16225 ,  H01L2924/14

    摘要： An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

    摘要翻译： 描述了与安装在IC封装上的集成电路（IC）一起使用的阵列电容器。 阵列电容器包括与多个第二导电层交错的多个第一导电层和分隔相邻导电层的多个电介质层。 阵列电容器还包括多个用于电连接第一导电层的第一导电通孔和多个第二导电通孔，以电连接第二导电层。 阵列电容器设置有开口，其被配置为使得IC封装的引脚能够通过。

    Selective plating of package terminals
    9.
    发明授权
    Selective plating of package terminals 有权
    包装端子的选择性电镀

    公开(公告)号：US07321172B2

    公开(公告)日：2008-01-22

    申请号：US11227532

    申请日：2005-09-14

    申请人： Dustin P. Wood ,  Debendra Mallik

    发明人： Dustin P. Wood ,  Debendra Mallik

    IPC分类号： H01L23/48

    CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

    摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

    摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。