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公开(公告)号：US08441497B1
公开(公告)日：2013-05-14
申请号：US11890838
申请日：2007-08-07
CPC分类号： G06T15/005 , G06T15/20
摘要： Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.
摘要翻译： 可以为图形原语访问顶点数据。 顶点数据包括基元的每个顶点的均匀坐标。 均匀坐标可用于确定通过原语区域归一化的透视校正重心坐标。 可以使用归一化的透视校正重心坐标来确定像素的属性的内插值。 这些操作可以使用在硬件中实现的加法器和乘法器执行。
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12.发明授权Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline 有权用于在图形管线的光栅阶段中实现钳位的z值插值的方法和系统公开(公告)号：US08432394B1
公开(公告)日：2013-04-30
申请号：US10845992
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method of computing z parameters for pixels of a geometric primitive. The method includes the step of accessing the geometric primitive comprising a plurality of vertices, wherein each vertex comprises a plurality of associated parameters including a depth parameter, z. During rasterization of the geometric primitive, respective z values are interpolated for each pixel of the geometric primitive. Each z value is represented within a predefined numerical range which substantially corresponds to a depth range between a near plane and a far plane related to pixel rendering. During the interpolating, the z values are allowed to exceed the predefined numerical range and roll over within the predefined numerical range. A multi-bit indicator is used to indicate when a z value for a pixel is outside of the depth range.
摘要翻译： 一种计算几何图元像素的z参数的方法。 该方法包括访问包括多个顶点的几何图元的步骤，其中每个顶点包括多个相关参数，包括深度参数z。 在几何图元的光栅化期间，对于几何图元的每个像素插入相应的z值。 每个z值被表示在预定的数值范围内，其基本上对应于与像素渲染相关的近平面和远平面之间的深度范围。 在内插期间，允许z值超过预定义的数值范围，并在预定义的数值范围内翻转。 多位指示器用于指示像素的z值何时超出深度范围。
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13.发明授权公开(公告)号：US08416242B1
公开(公告)日：2013-04-09
申请号：US10846786
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
IPC分类号： G06T17/00
CPC分类号： G06T15/00 , G06T11/40 , G06T2210/36
摘要： A method determining LOD values for a geometric primitive, in accordance with one embodiment of the present invention, includes accessing a plurality of geometric parameters of a vertex. An LOD value for a vertex is calculated as a function of the plurality of parameters of the vertex in a setup module. In a raster module an LOD value for a pixel is interpolated as a function of the LOD value of the pixel corresponding to the vertex and a view distance of the non-vertex pixel.
摘要翻译： 根据本发明的一个实施例，确定几何图元的LOD值的方法包括访问顶点的多个几何参数。 根据设置模块中的顶点的多个参数计算顶点的LOD值。 在光栅模块中，将像素的LOD值作为与顶点对应的像素的LOD值和非顶点像素的视距进行插值。
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公开(公告)号：US08040357B1
公开(公告)日：2011-10-18
申请号：US11893418
申请日：2007-08-15
IPC分类号： G09G5/00
CPC分类号： G06T11/40
摘要： Embodiments of the present invention pixel processing system and method provide convenient and efficient processing of pixel information. In one embodiment, quotient-remainder information associated with barycentric coordinate information indicating the location of a pixel is received. In one exemplary implementation quotient-remainder information is associated with barycentric coordinate information through the relationship c divided by dcdx, where c is the barycentric coordinate for a particular edge and dcdx is the derivative of the barycentric coordinate in the screen horizontal direction. The relationship of a pixel with respect to a primitive edge is determined based upon the quotient-remainder information. For example, a positive quotient can indicate a pixel is inside a triangle and a negative quotient can indicate a pixel is outside a triangle. Pixel processing such as shading is performed in accordance with the relationship of the pixel to the primitive.
摘要翻译： 本发明的像素处理系统和方法的实施例提供了对像素信息的方便和有效的处理。 在一个实施例中，接收与指示像素的位置的重心坐标信息相关联的商剩余信息。 在一个示例性实施方案中，商余数信息通过除以dcdx的关系c与重心坐标信息相关联，其中c是特定边缘的重心坐标，dcdx是屏幕水平方向上的重心坐标的导数。 基于商余数信息确定像素与原始边缘的关系。 例如，正商可以指示像素在三角形内，而负商可以指示像素在三角形之外。 根据像素与原图的关系来执行诸如阴影的像素处理。
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15.发明授权System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories 有权用于包含通用高速缓存存储器的3-D图形管线中的通用数据写入单元的系统和方法公开(公告)号：US07724263B2
公开(公告)日：2010-05-25
申请号：US10846774
申请日：2004-05-14
申请人： Edward A. Hutchins , Paul Kim , Brian K. Angell
发明人： Edward A. Hutchins , Paul Kim , Brian K. Angell
CPC分类号： G06F12/0875 , G06T1/60 , G06T15/005
摘要： A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.
摘要翻译： 一种用于包含通用高速缓冲存储器的3-D图形管线中的数据写入单元的系统和方法。 具体地，在一个实施例中，数据写入单元包括第一存储器，多个高速缓冲存储器和数据写入电路。 第一存储器接收与像素相关联的像素分组。 像素分组包括与像素的表面特性有关的数据。 多个高速缓冲存储器耦合到第一存储器，用于存储与多个像素的多个表面特性相关联的像素信息。 多个高速缓冲存储器中的每一个可编程地与指定的表面特性相关联。 数据写入电路耦合到第一个存储器和多个高速缓存存储器。 数据写入电路在程序控制下可操作以获得用于存储到多个高速缓冲存储器中的像素分组的指定部分。
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公开(公告)号：US09183607B1
公开(公告)日：2015-11-10
申请号：US11893431
申请日：2007-08-15
申请人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
发明人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
CPC分类号： G06T15/005 , G06T1/60 , G06T11/40
摘要： A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.
摘要翻译： 一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素。 存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。 缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。 比较来自缓冲的ID和片段数据以确定它们是否彼此对应。 当ID和片段数据匹配并且片段数据被写入存储器时，对多个像素中的每一个的参数评估的完成进行了说明。
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17.发明授权Reducing instruction execution passes of data groups through a data operation unit 有权通过数据操作单元减少数据组的指令执行次数公开(公告)号：US08856499B1
公开(公告)日：2014-10-07
申请号：US11893615
申请日：2007-08-15
申请人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
发明人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
CPC分类号： G06F9/3836 , G06F9/321 , G06F9/381 , G06F9/383
摘要： An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.
摘要翻译： 公开了一种装置。 该装置包括指令映射表，其包括多个指令计数和多个指令指针，每个指令指针与指令计数之一相对应。 每个指令指针标识下一个执行指令。 此外，每个指令计数指定从下一条指令开始执行的指令数。 该装置还具有数据操作单元，该数据操作单元适于接收数据组并适于在接收到的数据组上执行指令映射表的当前指令计数指定的指令数，该指令开始于由当前指令指针 在进行另一个数据组之前的指令映射表。
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公开(公告)号：US08594441B1
公开(公告)日：2013-11-26
申请号：US11520144
申请日：2006-09-12
CPC分类号： G06T9/00 , H04N1/646 , H04N19/124 , H04N19/136 , H04N19/186
摘要： Image-based data, such as a block of texel data, is accessed. The data includes sets of color component values. A luminance value is computed for each set of color components values, generating a range of luminance values. A first set and a second set of color component values that correspond to the minimum and maximum luminance values are selected from the sets of color component values. A third set of color component values can be mapped to an index that identifies how the color component values of the third set can be decoded using the color component values of the first and second sets. The index value is selected by determining where the luminance value for the third set lies in the range of luminance values.
摘要翻译： 访问基于图像的数据，例如一组纹素数据。 数据包括彩色分量值集合。 为每组颜色分量值计算亮度值，产生亮度值范围。 从颜色分量值的集合中选择对应于最小和最大亮度值的第一组和第二组颜色分量值。 可以将第三组颜色分量值映射到识别如何使用第一和第二组的颜色分量值来解码第三组的颜色分量值的索引。 通过确定第三组的亮度值位于亮度值的范围内来选择索引值。
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公开(公告)号：US20120206447A1
公开(公告)日：2012-08-16
申请号：US13370184
申请日：2012-02-09
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
CPC分类号： G06T15/005
摘要： Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.
摘要翻译： 简而言之，根据一个或多个实施例，可重构3D图形处理器包括流水线配置管理器，光栅化器和耦合到三角形光栅器的存储器。 管线配置管理器能够将图形处理器配置为以直接光栅化模式或平铺模式操作以处理从处理单元接收的绘图命令序列。
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20.发明申请公开(公告)号：US20110254848A1
公开(公告)日：2011-10-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译： 图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。 每个时钟周期，缓冲存储一行一系列像素数据。 在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。 在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。
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