公开(公告)号：US20230146470A1

公开(公告)日：2023-05-11

申请号：US18091728

申请日：2022-12-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H10B43/27 ,  G11C16/04 ,  H10B41/27 ,  H10B43/40 ,  H10B43/50 ,  H10B43/20 ,  H01L27/105 ,  H01L29/51

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/1052 ,  H01L29/513 ,  H01L27/11551

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritahle memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of colunmar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20220139955A1

公开(公告)日：2022-05-05

申请号：US17576164

申请日：2022-01-14

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Junya MATSUNAMI ,  Tomoko FUJIWARA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20210126012A1

公开(公告)日：2021-04-29

申请号：US17141534

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.