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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL
    2.
    发明公开
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL 审中-公开

    公开(公告)号：US20240120395A1

    公开(公告)日：2024-04-11

    申请号：US18537954

    申请日：2023-12-13

    Applicant: KIOXIA CORPORATION

    Inventor： Megumi ISHIDUKI ,  Hiroshi NAKAKI ,  Takamasa ITO

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

    CPC classification number: H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H01L23/528

    Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250079306A1

    公开(公告)日：2025-03-06

    申请号：US18755786

    申请日：2024-06-27

    Applicant: Kioxia Corporation

    Inventor： Megumi ISHIDUKI

    IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27

    Abstract: A semiconductor memory device includes conductive layers stacked in a stacking direction, a semiconductor column opposed to the conductive layers, a semiconductor member connected to the semiconductor column, a contact electrode connected to the semiconductor member, a first insulating member separating a part of the conductive layers in a first direction, and a second insulating member disposed inside the first insulating member. The contact electrode includes a first conductive region provided at an opposite side of the semiconductor column in the stacking direction with respect to a surface of the semiconductor member at the contact electrode side in the stacking direction and a second conductive region provided at a semiconductor column side in the stacking direction with respect to the surface of the semiconductor member between the semiconductor member and the second insulating member. The second conductive region is in contact with the second insulating member.

    SEMICONDUCTOR STORAGE DEVICE
    4.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20230307323A1

    公开(公告)日：2023-09-28

    申请号：US17901812

    申请日：2022-09-01

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi NAKAKI ,  Megumi ISHIDUKI

    IPC: H01L23/48 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

    CPC classification number: H01L23/481 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

    Abstract: A semiconductor storage device includes a stacked body in which conductive and insulating layers are alternately stacked in a first direction, conductive lines extending along a second direction intersecting the first direction and arranged along a third direction intersecting the first and second directions, insulators extending along the first and third directions in the body, arranged along the second direction, and dividing conductive layers, columnar bodies extending along the first direction and arranged along the second direction between insulators, each columnar body including a semiconductor body forming memory cells, and vias each connected between a conductive line and a corresponding columnar body. The conductive lines include first through fourth lines, and the columnar bodies include first through fourth bodies, arranged in this order. When viewed from the first direction, the first through fourth columnar bodies respectively overlap and are electrically connected to the first, third, second, and fourth lines.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250040135A1

    公开(公告)日：2025-01-30

    申请号：US18913023

    申请日：2024-10-11

    Applicant: KIOXIA CORPORATION

    Inventor： Megumi ISHIDUKI

    IPC: H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

    Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive layers stacked to be apart from each other in a first direction, and including a stair-like end with rising parts and terrace parts, wherein successive first conductive layers including an uppermost conductive layer function as select gate lines for a NAND string, and a first contact connected to the uppermost conductive layer provided to correspond to a first rising part which is an uppermost one of the rising parts. The first contact passes through the uppermost conductive layer to be further connected to a first conductive layer adjacent to the uppermost conductive layer.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220093633A1

    公开(公告)日：2022-03-24

    申请号：US17201064

    申请日：2021-03-15

    Applicant: Kioxia Corporation

    Inventor： Megumi ISHIDUKI

    IPC: H01L27/11578 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157

    Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive layers stacked to be apart from each other in a first direction, and including a stair-like end with rising parts and terrace parts, wherein successive first conductive layers including an uppermost conductive layer function as select gate lines for a NAND string, and a first contact connected to the uppermost conductive layer provided to correspond to a first rising part which is an uppermost one of the rising parts. The first contact passes through the uppermost conductive layer to be further connected to a first conductive layer adjacent to the uppermost conductive layer.

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