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11.发明申请Statistical Overlay Error Prediction for Feed Forward and Feedback Correction of Overlay Errors, Root Cause Analysis and Process Control 审中-公开统计叠加误差预测的前馈和反馈校正重叠错误，根本原因分析和过程控制公开(公告)号：US20170017162A1
公开(公告)日：2017-01-19
申请号：US15123980
申请日：2015-03-05
Applicant: KLA-Tencor Corporation
Inventor： Wei Chang , Krishna Rao , Joseph Gutierrez , Ramon Olavarria , Craig MacNaughton , Amir Azordegan , Prasanna Dighe
CPC classification number: G03F7/705 , G03F1/144 , G03F1/36 , G03F7/70633 , G06F17/5068 , G06F17/5081 , G06F2217/12 , G06N5/04 , G06N20/00 , Y02P90/265
Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.
Abstract translation: 收集数据和训练，验证和部署统计模型以使用图案化晶片几何数据和其他相关信息来预测覆盖误差的方法包括选择训练晶片组，在多个光刻步骤测量并计算几何差异，将多个预测模型应用于 训练晶片几何差异并将预测覆盖与训练晶片组上测量的覆盖层进行比较。 识别最准确的预测模型，并将结果反馈到光刻扫描仪工具，可以校正这些影响并减少晶片扫描和曝光过程中的重叠误差。
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12.发明申请Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance 有权基于增强图案化晶圆几何测量的设计改进，优化集成芯片制造性能公开(公告)号：US20160071260A1
公开(公告)日：2016-03-10
申请号：US14520998
申请日：2014-10-22
Applicant: KLA-Tencor Corporation
Inventor： Amir Azordegan , Pradeep Vukkadala , Craig MacNaughton , Jaydeep Sinha
CPC classification number: G01N21/9501 , G01B11/24 , G01N21/956 , G06T3/4069
Abstract: Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.
Abstract translation: 公开了能够对图案化晶片进行超高分辨率地形测量的方法和系统。 可以利用超高分辨率测量获得的测量来提高晶片度量测量精度。 此外，利用超高分辨率度量获得的测量结果也可用于提供反馈和/或校准控制以改善晶片的制造和设计。
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