摘要:
The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by immersion in and/or double sided brush scrubbing with a chemical agent. Embodiments include removing controlled portions up to 50 Å of silicon oxide by immersion in and/or double sided brush scrubbing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and dionized water.
摘要:
An improved method and apparatus for Chemical Mechanical Polishing (CMP) in integrated circuit processing utilizes a film measurement feedback loop for progressively optimizing the polishing pad conditioning recipe. By utilizing this invention, non-uniform pad wearing and elastic property variations are substantially corrected, and Within-Wafer-Non-Uniformity (WIWNU) is minimized.
摘要:
A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.
摘要:
A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.
摘要:
A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.
摘要:
A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要:
Disclosed heroin are an anti-counterfeiting film and a process for preparation thereof. The anti-counterfeiting film comprises a protective layer (1), a binder layer (2), a retroreflective layer (3), a photopolymerizable information layer (4) and a reflective layer (5) which are combined in turn. The retroreflective layer (3) is embedded spherically in the binder layer (2), and the photopolymerizable information layer (4) has been recorded with graphics information which can change along with the viewing angle.
摘要:
A method for the polarization independent frequency domain equalization (FDE) chromatic dispersion compensation on polarization multiplexing (POLMUX) coherent systems. Operationally, time domain signals are converted to frequency domain signals such that time domain convolution can be done as simple multiplications in the frequency domain. These frequency domain signals then converted back to time domain for subsequent use. The input signal size and FFT size are advantageously designed so that the output signals can be continuous with some overlap between two successive frames.
摘要:
Systems and methods are disclosed to allocate resources in discrete Fourier transform spread orthogonal frequency division multiple access (DFT-S-OFDMA) networks, which involve determining a reward for each user when assigned a frequency chunk (FC) of subcarriers, where each FC is a set of contiguous subcarriers; splitting each user into one or more sub-users, with each sub-user having identical rewards; and assigning resources with a message-passing based FC allocation.
摘要:
A CABAC decoding system includes at least a decoding unit group. Each decoding unit group includes N decoding units connected with each other. The Mth decoding unit receives parameter information for decoding bins and bit streams to be decoded, decodes the bins of the bit streams to be decoded, obtains the decoding result of the current decoding unit bin, and sends the updated parameter information to the (M+1)th decoding unit and an output unit. The CABAC decoding system achieves high decoding rate and keeps a reasonable cost of hardware resource, and thereby provides a high efficient and reasonable decoding solution.