Preventing Cu dendrite formation and growth
    11.
    发明授权
    Preventing Cu dendrite formation and growth 有权
    防止Cu枝晶的形成和生长

    公开(公告)号:US06177349B1

    公开(公告)日:2001-01-23

    申请号:US09206169

    申请日:1998-12-07

    IPC分类号: H01L2144

    CPC分类号: H01L21/7684 H01L21/76819

    摘要: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by immersion in and/or double sided brush scrubbing with a chemical agent. Embodiments include removing controlled portions up to 50 Å of silicon oxide by immersion in and/or double sided brush scrubbing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and dionized water.

    摘要翻译: 从Cu或Cu合金线发射到边界开放介质场中的枝晶的形成和/或生长通过从介电场中化学去除表面的一部分和CMP之后的线之间的浸入和/ 或用化学试剂双面刷洗。 实施例包括通过用含有氟化铵,柠檬酸氢铵,柠檬酸三铵,表面活性剂和二价离子水的溶液浸渍和/或双面刷洗来去除高达50埃的氧化硅的受控部分。

    Feedback loop for selective conditioning of chemical mechanical
polishing pad
    12.
    发明授权
    Feedback loop for selective conditioning of chemical mechanical polishing pad 失效
    用于化学机械抛光垫选择性调节的反馈回路

    公开(公告)号:US6113462A

    公开(公告)日:2000-09-05

    申请号:US993439

    申请日:1997-12-18

    申请人: Kai Yang

    发明人: Kai Yang

    CPC分类号: B24B53/017 B24B37/005

    摘要: An improved method and apparatus for Chemical Mechanical Polishing (CMP) in integrated circuit processing utilizes a film measurement feedback loop for progressively optimizing the polishing pad conditioning recipe. By utilizing this invention, non-uniform pad wearing and elastic property variations are substantially corrected, and Within-Wafer-Non-Uniformity (WIWNU) is minimized.

    摘要翻译: 用于集成电路处理中的化学机械抛光(CMP)的改进方法和装置利用膜测量反馈回路逐渐优化抛光垫调节配方。 通过利用本发明,基本上校正了不均匀的垫磨损和弹性变化,并且使晶片间非均匀性(WIWNU)最小化。

    Video decoder with multi-format vector processor and methods for use therewith
    13.
    发明授权
    Video decoder with multi-format vector processor and methods for use therewith 有权
    具有多格式矢量处理器的视频解码器及其使用方法

    公开(公告)号:US09503741B2

    公开(公告)日:2016-11-22

    申请号:US13162265

    申请日:2011-06-16

    摘要: A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.

    摘要翻译: 多格式视频解码器包括从编码视频信号生成熵解码(EDC)数据的熵解码装置。 多格式视频解码装置包括存储模块,存储多个操作指令,包括至少一个包括矩阵输入配置数据的矩阵乘法指令。 多个矢量处理器单元从EDC数据生成解码视频信号,其中多个矢量处理器中的至少一个包括矩阵乘法器,该矩阵乘法器根据第一输入数据和第二输入数据的乘法来生成输出数据, 矩阵输入配置数据,其中矩阵输入配置数据指示第一输入数据和第二输入数据的维度。

    VIDEO DECODER WITH MULTI-FORMAT VECTOR PROCESSOR AND METHODS FOR USE THEREWITH
    14.
    发明申请
    VIDEO DECODER WITH MULTI-FORMAT VECTOR PROCESSOR AND METHODS FOR USE THEREWITH 有权
    具有多格式矢量处理器的视频解码器及其使用方法

    公开(公告)号:US20120314774A1

    公开(公告)日:2012-12-13

    申请号:US13162265

    申请日:2011-06-16

    IPC分类号: H04N7/26

    摘要: A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.

    摘要翻译: 多格式视频解码器包括从编码视频信号生成熵解码(EDC)数据的熵解码装置。 多格式视频解码装置包括存储模块,存储多个操作指令,包括至少一个包括矩阵输入配置数据的矩阵乘法指令。 多个矢量处理器单元从EDC数据生成解码视频信号,其中多个矢量处理器中的至少一个包括矩阵乘法器,该矩阵乘法器根据第一输入数据和第二输入数据的乘法来生成输出数据, 矩阵输入配置数据,其中矩阵输入配置数据指示第一输入数据和第二输入数据的维度。

    MULTI-FUNCTION ENCODER AND DECODER DEVICES, AND METHODS THEREOF
    15.
    发明申请
    MULTI-FUNCTION ENCODER AND DECODER DEVICES, AND METHODS THEREOF 有权
    多功能编码器和解码器装置及其方法

    公开(公告)号:US20120147017A1

    公开(公告)日:2012-06-14

    申请号:US12965109

    申请日:2010-12-10

    IPC分类号: G06T1/20 G09G5/36

    摘要: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

    摘要翻译: 用于对视频信息进行编码和解码的技术使用多个视频处理模块(VPM),由此每个视频处理模块专用于特定的视频处理功能,例如滤波,矩阵算术运算等。 使用一组先进先出(FIFO)缓冲器在视频处理模块之间传送信息。 例如,为了将像素信息从第一VPM传送到第二VPM,第一VPM将像素信息存储在FIFO缓冲器的头部,而第二VPM从FIFO缓冲器的尾部检索信息。 因此,FIFO缓冲器允许在VPM之间传送信息,而不将信息存储到高速缓存或可以降低视频处理速度的其他技术。

    Power-aware debugging
    16.
    发明授权
    Power-aware debugging 有权
    电源感知调试

    公开(公告)号:US08176453B2

    公开(公告)日:2012-05-08

    申请号:US12558259

    申请日:2009-09-11

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5022 G06F2217/78

    摘要: A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

    摘要翻译: 调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。 该IC设计包括描述IC的IC的硬件描述语言(HDL)模型,其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言(PDML)模型。 调试系统产生表示HDL代码的显示器,其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。 调试系统还生成信号跟踪显示,指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

    POLARIZATION INDEPENDENT FREQUENCY DOMAIN EQUALIZATION (FDE) FOR CHROMATIC DISPERSION (CD) COMPENSATION IN POLMUX COHERENT SYSTEMS
    18.
    发明申请
    POLARIZATION INDEPENDENT FREQUENCY DOMAIN EQUALIZATION (FDE) FOR CHROMATIC DISPERSION (CD) COMPENSATION IN POLMUX COHERENT SYSTEMS 有权
    用于POLMUX相关系统中色散(CD)补偿的独立频域均衡(FDE)偏振

    公开(公告)号:US20100196009A1

    公开(公告)日:2010-08-05

    申请号:US12607125

    申请日:2009-10-28

    IPC分类号: H04J14/06

    摘要: A method for the polarization independent frequency domain equalization (FDE) chromatic dispersion compensation on polarization multiplexing (POLMUX) coherent systems. Operationally, time domain signals are converted to frequency domain signals such that time domain convolution can be done as simple multiplications in the frequency domain. These frequency domain signals then converted back to time domain for subsequent use. The input signal size and FFT size are advantageously designed so that the output signals can be continuous with some overlap between two successive frames.

    摘要翻译: 一种用于偏振复用(POLMUX)相干系统上的偏振独立频域均衡(FDE)色散补偿的方法。 在操作上,时域信号被转换成频域信号,使得时域卷积可以作为频域中的简单乘法来完成。 然后,这些频域信号被转换回到时域以供后续使用。 有利地设计输入信号尺寸和FFT尺寸,使得输出信号可以是连续的,在两个连续帧之间具有一些重叠。

    DISTRIBUTED MESSAGE-PASSING BASED RESOURCE ALLOCATION IN WIRELESS SYSTEMS
    19.
    发明申请
    DISTRIBUTED MESSAGE-PASSING BASED RESOURCE ALLOCATION IN WIRELESS SYSTEMS 有权
    基于分布式消息传递的无线系统资源分配

    公开(公告)号:US20100091729A1

    公开(公告)日:2010-04-15

    申请号:US12549546

    申请日:2009-08-28

    IPC分类号: H04W72/04 H04L27/28

    摘要: Systems and methods are disclosed to allocate resources in discrete Fourier transform spread orthogonal frequency division multiple access (DFT-S-OFDMA) networks, which involve determining a reward for each user when assigned a frequency chunk (FC) of subcarriers, where each FC is a set of contiguous subcarriers; splitting each user into one or more sub-users, with each sub-user having identical rewards; and assigning resources with a message-passing based FC allocation.

    摘要翻译: 公开了系统和方法来分配离散傅立叶变换扩展正交频分多址(DFT-S-OFDMA)网络中的资源,这些网络涉及当分配子载波的频率块(FC)时确定每个用户的奖励,其中每个FC 一组连续的副载波; 将每个用户分成一个或多个子用户,每个子用户具有相同的奖励; 并使用基于消息传递的FC分配来分配资源。

    Decoding system and method based on context-based adaptive binary arithmetic coding
    20.
    发明授权
    Decoding system and method based on context-based adaptive binary arithmetic coding 有权
    基于上下文的自适应二进制算术编码的解码系统和方法

    公开(公告)号:US07385535B2

    公开(公告)日:2008-06-10

    申请号:US11580734

    申请日:2006-10-12

    IPC分类号: H03M7/00

    摘要: A CABAC decoding system includes at least a decoding unit group. Each decoding unit group includes N decoding units connected with each other. The Mth decoding unit receives parameter information for decoding bins and bit streams to be decoded, decodes the bins of the bit streams to be decoded, obtains the decoding result of the current decoding unit bin, and sends the updated parameter information to the (M+1)th decoding unit and an output unit. The CABAC decoding system achieves high decoding rate and keeps a reasonable cost of hardware resource, and thereby provides a high efficient and reasonable decoding solution.

    摘要翻译: CABAC解码系统至少包括解码单元组。 每个解码单元组包括彼此连接的N个解码单元。 解码单元接收用于解码要解码的存储块和比特流的参数信息,对要解码的比特流的bin进行解码,获得当前解码单元bin的解码结果,并发送 更新参数信息到(M + 1)第个解码单元和输出单元。 CABAC解码系统实现了高解码率,保持了硬件资源的合理成本,从而提供了高效,合理的解码解决方案。