公开(公告)号：US4894684A

公开(公告)日：1990-01-16

申请号：US166004

申请日：1988-03-09

Applicant: Hisao Nakajima ,  Ken Tanabe

Inventor： Hisao Nakajima ,  Ken Tanabe

IPC: G03G15/01 ,  G03G15/08

CPC classification number: G03G15/0126 ,  G03G15/0896

Abstract: An image forming apparatus includes a main assembly having a developing position, an opening for receiving and delivering developing devices and developing device transportation passage for communicating the developing position and the opening; a developing device accommodating device for accommodating a plurality of the developing devices and for supplying them to the opening; a detecting device for detecting a malfunction of an image forming operation; and a device for transporting the developing device to either the main assembly or the developing device accommodating device in response to detection by the detecting device.

Abstract translation: 图像形成装置包括具有显影位置的主组件，用于接收和传送显影装置的开口和用于连通显影位置和开口的显影装置输送通道; 显影装置容纳装置，用于容纳多个显影装置并将其供给到所述开口; 用于检测图像形成操作的故障的检测装置; 以及用于响应于检测装置的检测将显影装置传送到主组件或显影装置容纳装置的装置。

公开(公告)号：US08732684B2

公开(公告)日：2014-05-20

申请号：US13013450

申请日：2011-01-25

Applicant: Nobuaki Tojo ,  Ken Tanabe ,  Hidenori Matsuzaki

Inventor： Nobuaki Tojo ,  Ken Tanabe ,  Hidenori Matsuzaki

IPC: G06F9/45

CPC classification number: G06F8/52

Abstract: According to one embodiment, a first program code including a plurality of variables is converted to a second program code to be executed by a multi-core processor including a plurality of cores. Specifically, an access pattern of each variable in the first program code is decided. All variables in the first program code are classified into a plurality of groups each of which variables belong to the same access pattern. A member structure of each group having variables belonging to the same access pattern is created. Each member structure includes variables of one group. A route-pointer indicating an address (in a memory) of variables of the member structure is created. The variables in the first program code are converted to the member structure and the route-pointer (in the second program code) that indicate the variables. The second program code is outputted to the multi-core processor.

Abstract translation: 根据一个实施例，包括多个变量的第一程序代码被转换为由包括多个核的多核处理器执行的第二程序代码。 具体地，确定第一程序代码中的每个变量的访问模式。 第一程序代码中的所有变量被分类为多个组，每个变量都属于相同的访问模式。 创建具有属于相同访问模式的变量的每个组的成员结构。 每个成员结构包括一个组的变量。 指示指示成员结构变量的地址（在存储器中）的路由指针。 第一个程序代码中的变量被转换为指示变量的成员结构和路由指针（在第二个程序代码中）。 第二程序代码被输出到多核处理器。

公开(公告)号：US20120042304A1

公开(公告)日：2012-02-16

申请号：US13013450

申请日：2011-01-25

Applicant: Nobuaki Tojo ,  Ken Tanabe ,  Hidenori Matsuzaki

Inventor： Nobuaki Tojo ,  Ken Tanabe ,  Hidenori Matsuzaki

IPC: G06F9/45

CPC classification number: G06F8/52

Abstract: According to one embodiment, as to a first program code including a plurality of variables, an access pattern of each variable by a processor is decided. The first program code is converted to a second program code including a plurality of threads. Each thread is executed by one of a plurality of cores of the processor. The second program code includes, (a) a first member structure including variables decided as a first access pattern, (b) a first route-pointer indicating the first member structure, the first route-pointer having a first access property representing accessibility by a core to execute a first thread, (c) a second member structure including variables decided as a second access pattern, (d) a second route-pointer indicating the second member structure, the second route-pointer having a second access property representing accessibility by the core to execute the first thread and a core to execute a second thread.

Abstract translation: 根据一个实施例，对于包括多个变量的第一程序代码，决定处理器的每个变量的访问模式。 将第一程序代码转换为包括多个线程的第二程序代码。 每个线程由处理器的多个核心之一执行。 第二程序代码包括：（a）包括被确定为第一访问模式的变量的第一成员结构，（b）指示第一成员结构的第一路由指针，第一路由指针具有代表可访问性的第一访问属性 执行第一线程的核心，（c）包括被确定为第二访问模式的变量的第二成员结构，（d）指示所述第二成员结构的第二路由指针，所述第二路由指针具有表示可访问性的第二访问属性 执行第一个线程的核心和执行第二个线程的核心。

公开(公告)号：US20100075839A1

公开(公告)日：2010-03-25

申请号：US12564970

申请日：2009-09-23

Applicant: Hiroshi TANADA ,  Ken Tanabe

Inventor： Hiroshi TANADA ,  Ken Tanabe

IPC: B01J23/10

CPC classification number: B01D53/945 ,  B01D2255/10 ,  B01D2255/206 ,  B01D2255/2092 ,  B01D2255/908 ,  B01D2255/9207 ,  B01D2257/404 ,  B01D2257/502 ,  B01D2257/702 ,  B01D2258/014 ,  B01J21/04 ,  B01J23/63 ,  B01J35/1019 ,  B01J37/0203 ,  B01J37/0205 ,  B01J37/0209 ,  Y02T10/22

Abstract: An exhaust gas purification catalyst includes a catalytic layer constituted by a heap of particles each obtained by applying a thin film of an oxygen storage material containing ceria to the surface of a base made of a material having a high-specific surface area, and allowing a precious metal to be supported on the surface of the thin film of the oxygen storage material.

Abstract translation: 废气净化催化剂包括由堆积的颗粒构成的催化剂层，所述催化剂层通过将含有二氧化铈的储氧材料的薄膜施加到由具有高比表面积的材料制成的基材的表面上而获得， 贵金属负载在储氧材料薄膜的表面上。

公开(公告)号：US06713817B2

公开(公告)日：2004-03-30

申请号：US10004077

申请日：2001-10-30

Applicant: Nobutaka Kitagawa ,  Ken Tanabe

Inventor： Nobutaka Kitagawa ,  Ken Tanabe

IPC: H01L2362

CPC classification number: H01L27/0629

Abstract: A semiconductor integrated circuit system includes first and second semiconductor devices formed on a substrate and required to have properties the same as each other in operation. The first and second semiconductor devices respectively includes first and second channel regions arranged in a surface of the substrate, and first and second gate electrodes disposed on the first and second channel regions via gate insulating films. A relaxing structure is arranged to reduce fluctuations in the properties of the first and second semiconductor devices, the fluctuations being caused by the electrical effects of plasma when a plasma process is performed. The relaxing structure includes first and second short-circuiting elements respectively connected to the first and second wiring layers and equivalent to each other. The first and second short-circuiting elements are configured to short-circuit the first and second gate electrodes with the first and second channel regions, respectively.

Abstract translation: 半导体集成电路系统包括在基板上形成的第一和第二半导体器件，并且在操作中具有彼此相同的特性。 第一和第二半导体器件分别包括布置在衬底的表面中的第一和第二沟道区，以及经由栅极绝缘膜设置在第一和第二沟道区上的第一和第二栅电极。 布置放松结构以减少第一和第二半导体器件的性质的波动，这是由于当执行等离子体处理时由等离子体的电效应引起的波动。 松弛结构包括分别连接到第一和第二布线层并彼此相等的第一和第二短路元件。 第一和第二短路元件被配置为分别使第一和第二栅电极与第一和第二沟道区域短路。

公开(公告)号：US5796301A

公开(公告)日：1998-08-18

申请号：US739951

申请日：1996-10-30

Applicant: Ken Tanabe ,  Tadashi Nukui

Inventor： Ken Tanabe ,  Tadashi Nukui

IPC: H03F3/34 ,  H03F3/45

CPC classification number: H03F3/45479

Abstract: An offset cancellation circuit of this invention includes operational amplifiers 11, 12 having fully differential outputs and common mode output, and comprises an adder 15 supplied with one Vo.sup.+ 1 of the fully-differential outputs of the operational amplifier 11 and one Vo.sup.+ 2 of the fully-differential outputs of the operational amplifier 12 to add them to output added result, an adder 16 supplied with the other Vo.sup.- 1 of the fully-differential outputs of the operational amplifier 11 and the other Vo.sup.- 2 of the fully-differential outputs of the operational amplifier 12 to add them to output added result, an adder 13 supplied with common mode output Vcm1 of the operational amplifier 11 and common mode output Vcm2 of the operational amplifier 12 to add them to output added result, and a multiplier 14 for multiplying an output of the adder 13 by 1/2 to output it. Thus, it is possible to eliminate influence of error resulting from offset quantities existing in respective common mode output potentials in plural operational amplifiers having fully-differential outputs.

Abstract translation: 本发明的偏移消除电路包括具有完全差分输出和共模输出的运算放大器11,12，并且包括一个加法器15，该加法器15提供运算放大器11的全差分输出的一个Vo + 1和一个Vo + 运算放大器12的全差分输出以将它们相加以输出相加结果;加法器16提供运算放大器11的全差分输出的另一个Vo-1，以及全差分输出的另一个Vo-2 运算放大器12的输出以将它们相加以输出相加结果，加法运算放大器11的共模输出Vcm1和运算放大器12的共模输出Vcm2加到输出相加结果中，乘法器14 用于将加法器13的输出乘以+ E，fra 1/2 + EE输出。 因此，可以消除在具有全差分输出的多个运算放大器中存在于相应共模输出电位中的偏移量所产生的误差的影响。

公开(公告)号：US5545979A

公开(公告)日：1996-08-13

申请号：US521586

申请日：1995-08-30

Applicant: Tadashi Nukui ,  Ken Tanabe

Inventor： Tadashi Nukui ,  Ken Tanabe

IPC: H02J1/00 ,  G05F1/10 ,  G05F1/56 ,  G05F3/18 ,  G05F3/16 ,  G01R7/00

CPC classification number: G05F3/18

Abstract: A power source device including, a primary reference voltage generating device having a positive power source terminal connected to receive one of ground potential and a DC positive voltage and a negative power source terminal connected to receive a primary DC negative voltage for generating a primary reference voltage, a reference voltage generating device having a positive power source terminal connected to receive the DC positive voltage and a negative power source terminal connected to receive the primary reference voltage for generating a reference voltage, a positive voltage generating device for obtaining a difference between the reference voltage and the primary reference voltage and amplifying the difference to generate the DC positive voltage, a negative voltage generating device for inverting amplifying the DC positive voltage to generate a negative DC voltage, and an integrated circuit having a positive power source terminal connected to receive the DC positive voltage and a negative power source terminal connected to receive the DC negative voltage. The integrated circuit and the reference voltage generating device are integrated and formed on a n-type substrate, and the negative power source terminal of the integrated circuit is isolated from the negative power source terminal of the reference voltage generating device.

Abstract translation: 一种电源装置，包括：主基准电压产生装置，其具有连接以接收地电位的一个正电源端子和DC正电压;以及负电源端子，所述负电源端子被连接以接收用于产生主参考电压的初级DC负电压 一个参考电压产生装置，具有被连接以接收DC正电压的正电源端子和连接以接收用于产生参考电压的主参考电压的负电源端子;正电压产生装置，用于获得参考电压之间的差值 电压和初级参考电压，并放大差值以产生直流正电压;负电压产生装置，用于反相放大直流正电压以产生负直流电压;以及集成电路，具有正电源端子，用于接收 直流正电压和 连接用于接收直流负电压的负电源端子。 集成电路和参考电压产生装置集成并形成在n型衬底上，并且集成电路的负电源端子与参考电压产生装置的负电源端子隔离。

公开(公告)号：US4941018A

公开(公告)日：1990-07-10

申请号：US289521

申请日：1988-12-27

Applicant: Toshirou Kasamura ,  Masashi Ohashi ,  Toshihiko Kusumoto ,  Naoki Okuda ,  Nobukazu Sasaki ,  Yasunori Maeda ,  Akiyoshi Kimura ,  Katsumi Munenaka ,  Yoshikuni Toyama ,  Minoru Nada ,  Ken Tanabe ,  Masamichi Ikeda ,  Yasuhide Hishikawa ,  Takashi Ozawa

Inventor： Toshirou Kasamura ,  Masashi Ohashi ,  Toshihiko Kusumoto ,  Naoki Okuda ,  Nobukazu Sasaki ,  Yasunori Maeda ,  Akiyoshi Kimura ,  Katsumi Munenaka ,  Yoshikuni Toyama ,  Minoru Nada ,  Ken Tanabe ,  Masamichi Ikeda ,  Yasuhide Hishikawa ,  Takashi Ozawa

IPC: G03G15/01 ,  G03G15/08

CPC classification number: G03G15/0896 ,  G03G15/0126

Abstract: An image forming apparatus includes an image bearing member, image forming station for forming a latent image on the image bearing member, a conveying passage extending toward the image bearing member to guide a developing device, a first moving mechanism for engaging with the developing device in the conveying passage and moving it in a substantially horizontal plane, wherein the image bearing member, the latent image forming station, the conveying passage and the first moving mechanism are provided in a main body of the image forming apparatus, a device for accommodating a plurality of developing devices. The accommodating device is mounted to the main body, the accommodating device includes, a second moving mechanism for moving the developing device opposed to the conveying passage into the conveying passage in a substantially horizontal plane and an accommodating case having partition stages arranged substantially vertically for accommodating plural developing devices and movable together with the developing devices accommodated therein, and a driver for transmitting a driving force selectively to the first driving mechanism, the second driving mechanism and the accommodating case.

Abstract translation: 图像形成装置包括图像承载部件，用于在图像承载部件上形成潜像的图像形成工位，朝向图像承载部件延伸以引导显影装置的输送通道，用于与显影装置接合的第一移动机构 所述输送通道在基本上水平的平面中移动，其中所述图像承载部件，潜像形成工位，所述输送通道和所述第一移动机构设置在所述图像形成装置的主体中， 的开发设备。 容纳装置安装在主体上，容纳装置包括：第二移动机构，用于将基本上水平的平面中的与输送通道相对的显影装置移动到输送通道中;以及容纳壳体，具有大致垂直布置的分隔台， 多个显影装置，并且与容纳在其中的显影装置一起移动;以及驱动器，用于选择性地将驱动力传递到第一驱动机构，第二驱动机构和容纳壳体。

公开(公告)号：US4792828A

公开(公告)日：1988-12-20

申请号：US890411

申请日：1986-07-29

Applicant: Takashi Ozawa ,  Yasuyoshi Yamamoto ,  Masashi Ohashi ,  Akiyoshi Kimura ,  Nobukazu Sasaki ,  Toshirou Kasamura ,  Atsushi Kubota ,  Tatsuya Shiratori ,  Toshihiko Kusumoto ,  Michiro Koike ,  Ken Tanabe ,  Hidetoshi Tanaka

Inventor： Takashi Ozawa ,  Yasuyoshi Yamamoto ,  Masashi Ohashi ,  Akiyoshi Kimura ,  Nobukazu Sasaki ,  Toshirou Kasamura ,  Atsushi Kubota ,  Tatsuya Shiratori ,  Toshihiko Kusumoto ,  Michiro Koike ,  Ken Tanabe ,  Hidetoshi Tanaka

IPC: G03G15/00 ,  G03G15/01 ,  G03G15/041 ,  G03G15/36 ,  G03G21/00

CPC classification number: G03G15/5029 ,  G03G15/041 ,  G03G15/5095 ,  G03G2215/00578 ,  G03G2215/00586 ,  G03G2215/0059

Abstract: An image forming apparatus capable of effecting plural image forming operations on one transfer sheet includes an image transfer device for transferring an image on the transfer sheet, an image magnification changing mechanism for changing the magnification of the image to be transferred onto the transfer sheet, and a control device for controlling the magnification changing mechanism in accordance with deformation of the transfer sheet caused by an image forming operation on the transfer sheet, after a first image is formed on the transfer sheet and before a second image is formed on the same transfer sheet, whereby those images are correctly registered.

Abstract translation: 能够在一个转印纸上进行多个图像形成操作的图像形成装置包括用于转印转印纸上的图像的图像转印装置，用于改变要转印到转印纸上的图像的放大率的图像倍率改变机构，以及 控制装置，用于在转印纸上形成第一图像之后并且在将第二图像形成在同一转印纸上之前根据由转印纸上的图像形成操作引起的转印纸的变形来控制倍率改变机构 ，从而正确地注册那些图像。