公开(公告)号：US20060291297A1

公开(公告)日：2006-12-28

申请号：US11513394

申请日：2006-08-31

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/10

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

公开(公告)号：US20060007770A1

公开(公告)日：2006-01-12

申请号：US10968811

申请日：2004-10-20

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US08064264B2

公开(公告)日：2011-11-22

申请号：US11974295

申请日：2007-10-11

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

摘要翻译： 一种半导体器件，包括：包括非易失性存储单元的存储单元阵列; 包含在存储单元阵列中并存储区域数据的区域; 第一存储单元，保存从存储单元阵列传送的数据，并输出数据; 以及控制电路，其选择用于使所述第一存储单元保持从所述存储单元阵列传送的区域数据并输出所述区域数据的主读取模式;以及辅助读取模式，用于使所述第一存储单元保持多个 通过划分区域数据并从存储单元阵列传送而形成的分割数据并输出分割数据。

公开(公告)号：US20080098165A1

公开(公告)日：2008-04-24

申请号：US11974295

申请日：2007-10-11

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

IPC分类号： G06F12/00

CPC分类号： G11C16/26

摘要： A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

摘要翻译： 一种半导体器件，包括：包括非易失性存储单元的存储单元阵列; 包含在存储单元阵列中并存储区域数据的区域; 第一存储单元，保存从存储单元阵列传送的数据，并输出数据; 以及控制电路，其选择用于使所述第一存储单元保持从所述存储单元阵列传送的区域数据并输出所述区域数据的主读取模式;以及辅助读取模式，用于使所述第一存储单元保持多个 通过划分区域数据并从存储单元阵列传送而形成的分割数据并输出分割数据。

公开(公告)号：US08363466B2

公开(公告)日：2013-01-29

申请号：US12976355

申请日：2010-12-22

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

IPC分类号： G11C11/34

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

摘要： At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

摘要翻译： 在读取时，将未选择的字线电压固定为第一预定电压（0V或3V），并且当选择字线时，将所选字线电压设置为第二预定电压（-3.5V或 0 V）。 这种配置消除了在读取时对字线施加脉冲电压，从而可以减小读取干扰的影响。 此外，即使在读取时需要从电源电压到接地电压或电源电压以上的电压的电压，其变为电源电压绝对值的约1.5倍的电压 。 因此，不需要具有大量级的升压电路，结果，能够以低功耗实现缩短的动作时间。

公开(公告)号：US20110157978A1

公开(公告)日：2011-06-30

申请号：US12976355

申请日：2010-12-22

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

摘要： At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

摘要翻译： 在读取时，将未选择的字线电压固定为第一预定电压（0V或3V），并且当选择字线时，将所选字线电压设置为第二预定电压（-3.5V或 0 V）。 这种配置消除了在读取时对字线施加脉冲电压，从而可以减小读取干扰的影响。 此外，即使在读取时需要从电源电压到接地电压或电源电压以上的电压的电压，其变为电源电压绝对值的约1.5倍的电压 。 因此，不需要具有大量级的升压电路，结果，能够以低功耗实现缩短的动作时间。

公开(公告)号：US08553459B2

公开(公告)日：2013-10-08

申请号：US13081094

申请日：2011-04-06

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/22

摘要： A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

摘要翻译： 非易失性半导体存储器件包括：第一串，包括串联连接的第一数量的存储单元，以非易失性方式存储信息; 并且包括串联连接的第二数量的存储单元的第二串，其以非易失性方式存储信息，其中第二数小于第一数量。

公开(公告)号：US20110261622A1

公开(公告)日：2011-10-27

申请号：US13081094

申请日：2011-04-06

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Takahiro Hatada ,  Satoru Sugimoto ,  Satoshi Sakurakawa

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/22

摘要： A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

摘要翻译： 非易失性半导体存储器件包括：第一串，包括串联连接的第一数量的存储单元，以非易失性方式存储信息; 并且包括串联连接的第二数量的存储单元的第二串，其以非易失性方式存储信息，其中第二数小于第一数量。

公开(公告)号：US07471585B2

公开(公告)日：2008-12-30

申请号：US11508917

申请日：2006-08-24

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

公开(公告)号：US07113441B2

公开(公告)日：2006-09-26

申请号：US11057841

申请日：2005-02-15

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。