公开(公告)号：US07616519B2

公开(公告)日：2009-11-10

申请号：US11812193

申请日：2007-06-15

申请人： Shigenobu Komatsu ,  Masanao Yamaoka

发明人： Shigenobu Komatsu ,  Masanao Yamaoka

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/412

摘要： The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

摘要翻译： 本发明提供一种能够在安装有时间分配虚拟多端口存储器等的半导体集成电路装置上实现面积缩小的技术。 通过提供包括单端口存储器，用于多个端口的数据锁存电路，用于选择要连接到单端口存储器的端口的选择器，时间共享控制信号生成电路等，其中内部的操作终止信号 将单端口存储器（字线上升信号，用于数据读取的读出放大器驱动信号等）输入到时间共享控制信号发生电路，以产生用于单端口存储器的端口切换控制信号和操作控制信号 可以实现具有减小面积的虚拟多端口存储器的时间分配，这不需要新的时间分配控制的时钟发生电路。

公开(公告)号：US08054871B2

公开(公告)日：2011-11-08

申请号：US12370338

申请日：2009-02-12

申请人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

发明人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

IPC分类号： H04L5/16 ,  H04B1/38

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

公开(公告)号：US20090245445A1

公开(公告)日：2009-10-01

申请号：US12370338

申请日：2009-02-12

申请人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

发明人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

IPC分类号： H04L7/00

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

公开(公告)号：US08183899B2

公开(公告)日：2012-05-22

申请号：US12615607

申请日：2009-11-10

申请人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

发明人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

IPC分类号： H03L7/00

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03L7/0818 ,  H03L7/089 ,  Y02D10/126 ,  Y02D10/172

摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

公开(公告)号：US20100117697A1

公开(公告)日：2010-05-13

申请号：US12615607

申请日：2009-11-10

申请人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

发明人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03L7/0818 ,  H03L7/089 ,  Y02D10/126 ,  Y02D10/172

摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

公开(公告)号：US08350595B2

公开(公告)日：2013-01-08

申请号：US13438050

申请日：2012-04-03

申请人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

发明人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

IPC分类号： G01R25/00 ,  H03D13/00

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03L7/0818 ,  H03L7/089 ,  Y02D10/126 ,  Y02D10/172

摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

公开(公告)号：US20120187993A1

公开(公告)日：2012-07-26

申请号：US13438050

申请日：2012-04-03

申请人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

发明人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03L7/0818 ,  H03L7/089 ,  Y02D10/126 ,  Y02D10/172

摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。