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公开(公告)号:US20070143545A1
公开(公告)日:2007-06-21
申请号:US11671394
申请日:2007-02-05
申请人: Kevin Conley , Reuven Elhamias
发明人: Kevin Conley , Reuven Elhamias
CPC分类号: G06F12/0862 , G06F12/0804 , G06F12/0866 , G06F2212/2022 , G06F2212/214 , G06F2212/2146 , G06F2212/282 , G06F2212/502
摘要: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.
摘要翻译: 介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。 缓存策略包括直写,写入和预读。 直写和回写策略可能会提高速度。 预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。 会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。
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公开(公告)号:US20130151755A1
公开(公告)日:2013-06-13
申请号:US13323612
申请日:2011-12-12
申请人: Reuven Elhamias , Ram Fishler
发明人: Reuven Elhamias , Ram Fishler
IPC分类号: G06F12/00
CPC分类号: G06F3/0625 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2212/1028 , Y02D10/13
摘要: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.
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13.
公开(公告)号:US07917719B2
公开(公告)日:2011-03-29
申请号:US11566685
申请日:2006-12-04
申请人: Reuven Elhamias , David Zehavi , Roni Barzilai , Vivek Mani , Simon Stolero
发明人: Reuven Elhamias , David Zehavi , Roni Barzilai , Vivek Mani , Simon Stolero
IPC分类号: G06F12/00
CPC分类号: G06F13/385
摘要: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.
摘要翻译: 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效,可以欺骗总线超时要求(在任一方向上),从而允许执行可能超过特定规范的总线超时的更复杂的处理操作。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线,直到存储器系统即将超时。 在写入操作期间,控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块,导致总线超时周期被复位。 在读操作期间,控制器在读总线超时时间到期之前,向计算机系统发送伪数据块,导致总线超时时间被重置。
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公开(公告)号:US07814377B2
公开(公告)日:2010-10-12
申请号:US10888294
申请日:2004-07-09
申请人: Simon Stolero , Micky Holtzman , Yosi Pinto , Reuven Elhamias , Meiri Azari
发明人: Simon Stolero , Micky Holtzman , Yosi Pinto , Reuven Elhamias , Meiri Azari
CPC分类号: G06F11/267
摘要: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel.
摘要翻译: 在非易失性存储器系统中,测试数据可以通过电路在没有固件的帮助下检索。 当它检测到处理器或主机接口中的异常时,电路被触发成动作。 在这种情况下,它会从非易失性存储器系统控制器中的各个块格式化自检或状态信号,并且在没有系统处理器或接口控制器的帮助的情况下向外界发送测试消息。 当在具有多个数据线的存储器系统中实现时,只有一条数据线可以用于此目的,从而允许在系统仍在执行数据传输时执行测试。 优选地,系统包括测试模式通信控制器,其可以在测试信道和用于测试消息传送的主机接口信道之间进行选择,使得当存储器系统处于测试包中时也可以执行相同的测试 封装包装。 测试消息被重复发送,并且测试消息被构造为使得接收者主机更容易解密消息而不与存储器系统进行握手。 通信控制器优选地检测用于发送信号的非易失性存储器系统的控制器是否没有使用任何通信信道,并且通过这样的信道发送诊断信号。
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15.
公开(公告)号:US20090164681A1
公开(公告)日:2009-06-25
申请号:US11566685
申请日:2006-12-04
申请人: Reuven Elhamias , David Zehavi , Roni Barzilai , Vivek Mani , Simon Stolero
发明人: Reuven Elhamias , David Zehavi , Roni Barzilai , Vivek Mani , Simon Stolero
IPC分类号: G06F13/372
CPC分类号: G06F13/385
摘要: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.
摘要翻译: 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效,可以欺骗总线超时要求(在任一方向上),从而允许执行更复杂的处理操作,否则在超时时间段内可能不可靠。 这允许存储器系统在可能超过特定规范的总线超时的时间段内执行应用或处理数据。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线,直到存储器系统即将超时。 在写入操作期间,控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块,导致总线超时周期被复位。 在读操作期间,控制器在读总线超时时间到期之前,向计算机系统发送伪数据块,导致总线超时时间被重置。
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公开(公告)号:US20070230690A1
公开(公告)日:2007-10-04
申请号:US11397101
申请日:2006-04-03
申请人: Reuven Elhamias , Vivek Mani , Niv Cohen
发明人: Reuven Elhamias , Vivek Mani , Niv Cohen
CPC分类号: H04L9/0637 , H04L9/0894
摘要: When cipher block chaining encryption/decryption is employed, write fault recovery is accomplished by storing information useful for the writing of cipher block chaining processed data before it is written to storage cells. Hence when write failure is discovered, this information stored can be retrieved for rewriting the data to the cells. Preferably, the information stored includes security configuration information for cipher block chaining processing a unit of data.
摘要翻译: 当采用密码块链接加密/解密时,通过在将密码块链接处理的数据写入存储单元之前存储有用的写入信息来实现写入故障恢复。 因此,当发现写入失败时,可以检索存储的信息以将数据重写到单元。 优选地,存储的信息包括用于密码块链接处理数据单元的安全配置信息。
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公开(公告)号:US20070067684A1
公开(公告)日:2007-03-22
申请号:US10888294
申请日:2004-07-09
申请人: Simon Stolero , Micky Holtzman , Yosi Pinto , Reuven Elhamias , Meiri Azari
发明人: Simon Stolero , Micky Holtzman , Yosi Pinto , Reuven Elhamias , Meiri Azari
IPC分类号: G11C29/00
CPC分类号: G06F11/267
摘要: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel.
摘要翻译: 在非易失性存储器系统中,测试数据可以通过电路在没有固件的帮助下检索。 当它检测到处理器或主机接口中的异常时,电路被触发成动作。 在这种情况下,它会从非易失性存储器系统控制器中的各个块格式化自检或状态信号,并且在没有系统处理器或接口控制器的帮助的情况下向外界发送测试消息。 当在具有多个数据线的存储器系统中实现时,只有一条数据线可以用于此目的,从而允许在系统仍在执行数据传输时执行测试。 优选地,系统包括测试模式通信控制器,其可以在测试信道和用于测试消息传送的主机接口信道之间进行选择,使得当存储器系统处于测试包中时也可以执行相同的测试 封装包装。 测试消息被重复发送,并且测试消息被构造为使得接收者主机更容易解密消息而不与存储器系统进行握手。 通信控制器优选地检测用于发送信号的非易失性存储器系统的控制器是否没有使用任何通信信道,并且通过这样的信道发送诊断信号。
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公开(公告)号:US20060022054A1
公开(公告)日:2006-02-02
申请号:US10901849
申请日:2004-07-28
申请人: Reuven Elhamias , Andrew Tomlin , Wesley Brewer , Yosi Pinto , Micky Holtzman
发明人: Reuven Elhamias , Andrew Tomlin , Wesley Brewer , Yosi Pinto , Micky Holtzman
IPC分类号: G06K19/06
CPC分类号: G06F3/0607 , G06F3/0632 , G06F3/0679 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要: A memory card that adapts its operation according to the application to which it applied or the conditions under which it is operated. This allows the card to dynamical self optimize. In a first set of embodiments, the card uses host profiling where it will learn about the host during host-card interactions and the card's controller will optimize its algorithms accordingly. In another set of embodiments, the host and card will report to one another their capabilities for a quality of service negotiation. A further set of embodiments allows the storage device to memorize access sequences issued by the host under various predefined conditions, such as host reset or a power on boot sequence. The storage device can use this information to optimize operation for the expected commands. On deviation from an expected sequence, the device would memorize the new command sequence and save it, thus operating in a self-adaptive manner.
摘要翻译: 一种存储卡,根据其应用的应用或操作条件来适应其操作。 这样可以让卡片进行动态自我优化。 在第一组实施例中,卡使用主机分析,其中将在主机卡交互期间了解主机,并且卡的控制器将相应地优化其算法。 在另一组实施例中,主机和卡将彼此报告其服务质量协商的能力。 另一组实施例允许存储设备在诸如主机复位或引导顺序的电源的各种预定条件下存储由主机发出的访问序列。 存储设备可以使用该信息来优化预期命令的操作。 在偏离预期序列时,设备将记忆新的命令序列并保存,从而以自适应的方式运行。
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公开(公告)号:US10031850B2
公开(公告)日:2018-07-24
申请号:US13154751
申请日:2011-06-07
申请人: Reuven Elhamias
发明人: Reuven Elhamias
IPC分类号: G06F13/00 , G06F12/0862 , G06F12/0866
摘要: A data storage device includes a controller, a non-volatile memory, and a buffer accessible to the controller. The buffer is configured to store data retrieved from the non-volatile memory to be accessible to a host device in response to receiving from the host device one or more requests for read access to the non-volatile memory while the data storage device is operatively coupled to the host device. The controller is configured to read an indicator of cached data in response to receiving a request for read access to the non-volatile memory. The request includes a data identifier. In response to the indicator of cached data not indicating that data corresponding to the data identifier is in the buffer, the controller is configured to retrieve data corresponding to the data identifier as well as additional data from the non-volatile memory and to write the data corresponding to the data identifier and the additional data to the buffer. The controller is configured to update the indicator of cached data in response to retrieved data from the non-volatile memory being written to the buffer.
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公开(公告)号:US08292177B2
公开(公告)日:2012-10-23
申请号:US13047631
申请日:2011-03-14
申请人: Reuven Elhamias , Andrew Tomlin , Wesley G. Brewer , Yosi Pinto , Micky Holtzman
发明人: Reuven Elhamias , Andrew Tomlin , Wesley G. Brewer , Yosi Pinto , Micky Holtzman
IPC分类号: G06K7/08
CPC分类号: G06F3/0607 , G06F3/0632 , G06F3/0679 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要: A memory card that adapts its operation according to the application to which it applied or the conditions under which it is operated. This allows the card to dynamical self optimize. In a first set of embodiments, the card uses host profiling where it will learn about the host during host-card interactions and the card's controller will optimize its algorithms accordingly. In another set of embodiments, the host and card will report to one another their capabilities for a quality of service negotiation. A further set of embodiments allows the storage device to memorize access sequences issued by the host under various predefined conditions, such as host reset or a power on boot sequence. The storage device can use this information to optimize operation for the expected commands. On deviation from an expected sequence, the device would memorize the new command sequence and save it, thus operating in a self-adaptive manner.
摘要翻译: 一种存储卡,根据其应用的应用或操作条件来适应其操作。 这样可以让卡片进行动态自我优化。 在第一组实施例中,卡使用主机分析,其中将在主机卡交互期间了解主机,并且卡的控制器将相应地优化其算法。 在另一组实施例中,主机和卡将彼此报告其服务质量协商的能力。 另一组实施例允许存储设备在诸如主机复位或引导顺序的电源的各种预定条件下存储由主机发出的访问序列。 存储设备可以使用该信息来优化预期命令的操作。 在偏离预期序列时,设备将记忆新的命令序列并保存,从而以自适应的方式运行。
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