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公开(公告)号：US20120059996A1
公开(公告)日：2012-03-08
申请号：US12876366
申请日：2010-09-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0811
摘要： A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register.
摘要翻译： 提供了一种用于避免流数据优化的一级缓存的交叉询问的机制。 该机制添加了一组专用寄存器（称为“copex寄存器”）来跟踪协处理器的L1高速缓存保存的高速缓存行的所有权。 该机制将L2高速缓存的缓存目录扩展一个位，以识别协处理器高速缓存中高速缓存行的独占所有权。 协处理器连续提供哪些共享寄存器有效的指示。 对于需要在L2缓存中进行目录查找的任何操作，该机制将将有效的copex寄存器与查找地址并行地与目录查找进行比较。 该机制认为目录中的“独占所有权协同处理器”位只有当高速缓存行当前还在有效的copex寄存器中时才有效。
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公开(公告)号：US08082399B2
公开(公告)日：2011-12-20
申请号：US12184165
申请日：2008-07-31
申请人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
发明人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
IPC分类号： G06F13/376
CPC分类号： G06F12/0261 , G06F12/0802
摘要： Cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object “Z” is a valid reference, is in a cache, and has a continuity flag set to “on”. If the object “Z” is a valid reference, is in the cache, and has a continuity flag set to “on”, the object “O” is locked for an update, a reference counter is decremented for the object “Z” if the object “Z” resides in the cache, and a return code is set to zero to indicate that the object “Z” is de-referenced and that its storage memory can be released and re-used if the reference counter for the object “Z” reaches zero. Thereafter, the cache hardware is similarly queried regarding an object “N” that will become a new reference of object “O”.
摘要翻译： 具有自动存储器管理的计算机语言的缓存有界引用计数，其中例如对最初存储在对象“O”中的对象“Z”的引用被取出，并且查询高速缓存硬件是否对对象“Z”的引用 是一个有效的参考，位于缓存中，并具有设置为“开”的连续性标志。 如果对象“Z”是有效的引用，则在缓存中，并且连续性标志设置为“on”，则对象“O”被锁定以进行更新，对于对象“Z”，引用计数器递减if 对象“Z”驻留在高速缓存中，并且返回码被设置为零以指示对象“Z”被去引用，并且如果对象的引用计数器“可以释放和重新使用其存储存储器” Z“达到零。 此后，对于将成为对象“O”的新引用的对象“N”，类似地查询高速缓存硬件。
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公开(公告)号：US07783690B2
公开(公告)日：2010-08-24
申请号：US11390791
申请日：2006-03-28
IPC分类号： G06F15/00
CPC分类号： G06F7/766
摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.
摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。
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14.发明申请公开(公告)号：US20140082290A1
公开(公告)日：2014-03-20
申请号：US13621328
申请日：2012-09-17
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0844 , G06F12/0893 , G06F2212/1016 , G06F2212/6042
摘要： A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
摘要翻译： 在用于增强支持辅助数据输出的高速缓存的布线结构的数据处理系统中提供一种机制。 该机制将数据高速缓存分解成第一数据部分和第二数据部分。 第一数据部分提供第一组数据元素，第二数据部分提供第二组数据元素。 该机制连接第一数据路径以将第一组数据元素提供给主输出，并连接第二数据路径以将第二组数据元素提供给主输出。 该机构将第一数据路径馈送回第二数据路径并将第二数据路径馈送回第一数据路径。 该机制将辅助输出连接到第二数据路径。
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15.发明授权公开(公告)号：US08495452B2
公开(公告)日：2013-07-23
申请号：US13024775
申请日：2011-02-10
申请人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
发明人： Michael Fee , Christian Habermann , Christian Jacobi , Diana L. Orf , Martin Recktenwald , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.
摘要翻译： 在乱序处理环境中处理损坏的背景数据。 修改的数据存储在具有至少一个字节的背景数据的字的字节上。 一个字节有效向量和一个字节存储位被加到该字中。 对这个词进行奇偶校验。 如果该单词不包含损坏的背景日期，该单词将传播到下一级缓存。 如果该单词包含已损坏的背景数据，则该字的副本将从ECC保护的高级缓存中提取，具有修改后的数据的字节将从该字中提取出来并交换为字副本中的相应字节。 然后将该字复制到被保护的ECC缓存的下一级。
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16.发明授权Method, system, and computer program product for handling errors in a cache without processor core recovery 有权用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
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17.发明申请METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION 有权具有同步分辨率的多级虚拟/实时缓存系统的方法和系统公开(公告)号：US20090216949A1
公开(公告)日：2009-08-27
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
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18.发明申请Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel 失效用于控制数据信道中的不可靠数据传输的方法和装置公开(公告)号：US20090193308A1
公开(公告)日：2009-07-30
申请号：US12356191
申请日：2009-01-20
IPC分类号： G06F11/07
CPC分类号： H04L41/0654
摘要： Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.
摘要翻译： 控制从发送单元到接收单元的数据信道中的不可靠数据传输。 根据数据通道中的错误率，激活旁路模式或缓冲模式。 如果选择了旁路模式，则通过旁路线将数据分组从发送单元直接传送到接收单元。 数据包在数据传输后进行错误检查。 如果选择了缓冲模式，则经由错误检测和校正单元和缓冲器单元通过缓冲线将数据从发送单元传送到接收单元。 在数据传输期间检测和纠正错误。
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19.发明授权公开(公告)号：US07552286B2
公开(公告)日：2009-06-23
申请号：US12051012
申请日：2008-03-19
IPC分类号： G06F13/00
CPC分类号： G06F12/127
摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
摘要翻译： 一种用于提高缓存性能的方法和系统。 高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。 通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。 通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。
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20.发明申请公开(公告)号：US20080168236A1
公开(公告)日：2008-07-10
申请号：US12051012
申请日：2008-03-19
IPC分类号： G06F12/08
CPC分类号： G06F12/127
摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
摘要翻译： 一种用于提高缓存性能的方法和系统。 高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。 通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。 通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。
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