公开(公告)号：US06497993B1

公开(公告)日：2002-12-24

申请号：US09614010

申请日：2000-07-11

申请人： Yuan-Hunh Chiu ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Chu-Yun Fu

发明人： Yuan-Hunh Chiu ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Chu-Yun Fu

IPC分类号： G03F736

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： A process for forming a contact hole opening, featuring the use in situ dry etching, and photoresist removal procedures, used to define the desired contact hole opening; in an overlying hard mask layer, in the dielectric layer, and in an underlying insulator stop layer, has been developed. The process features the initial definition of the contact hole opening, in an overlying hard mask insulator layer, accomplished in a chamber of a dry etch tool, followed by removal of an overlying, contact hole defining photoresist shape, performed in situ, in the same dry etch chamber. The contact hole opening is then transferred to the dielectric layer via a selective dry etch procedure, performed in situ, in the dry etch chamber, using the overlying hard mask insulator layer as an etch mask. A final dry etch procedure is then performed in situ, in the same dry etch chamber, to form the contact hole opening in the underlying insulator stop layer, with the final dry etch procedure also resulting in the removal of the exposed hard mask insulator layer, thus creating the desired contact hole opening in a dielectric layer, and in the underlying insulator stop layer.

摘要翻译： 用于形成接触孔开口的方法，其特征在于使用原位干蚀刻和光致抗蚀剂去除程序，用于限定所需的接触孔开口; 在覆盖的硬掩模层，电介质层和下面的绝缘体停止层中已经开发出来。 该方法具有接触孔开口的初始定义，在覆盖的硬掩模绝缘体层中，在干蚀刻工具的腔室中完成，随后除去在相同的位置原位执行限定光致抗蚀剂形状的上覆接触孔 干蚀刻室。 接触孔开口然后通过选择性干蚀刻方法，在干蚀刻室中原位进行，使用覆盖的硬掩模绝缘体层作为蚀刻掩模转移到电介质层。 然后在相同的干蚀刻室中原位进行最终的干蚀刻工艺，以在下面的绝缘体停止层中形成接触孔开口，最终的干法蚀刻程序也导致暴露的硬掩模绝缘体层的去除， 从而在电介质层中和在下面的绝缘体停止层中产生所需的接触孔开口。

公开(公告)号：US06399483B1

公开(公告)日：2002-06-04

申请号：US09624523

申请日：2000-07-24

申请人： Jen-Cheng Liu ,  Ming-Huei Lui ,  Hun-Jan Tao ,  Chia Shiung Tsai

发明人： Jen-Cheng Liu ,  Ming-Huei Lui ,  Hun-Jan Tao ,  Chia Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76814 ,  H01L21/76808 ,  H01L2221/1063

摘要： A new method is provided for creating the interconnect pattern for dual damascene structures. The dual damascene structure is created in two overlying levels of dielectric, a first etch stop layer is deposited over the surface of the substrate, a second etch stop layer is deposited between the two layers of dielectric. A first etch penetrates both layers of dielectric, a second etch penetrates the top dielectric layer. Before the second etch is performed, a layer of ARC is deposited. For the second etch a polymer rich etchant is used to protect the sidewalls of the opening. The second etch leaves in place a fence of material (containing C, H, F and oxide compounds) that is formed around the upper perimeter of the opening through the lower layer of dielectric. This fence protects the upper corners of the lower opening of the dual damascene structure and is removed in a two step procedure. At the completion of this two step procedure the upper corners of the lower opening of the dual damascene structure have retained a rectangular profile. A final step removes the photoresist (that has been used to create the interconnect line opening) from the surface of the second layer of dielectric while the remnants of the ARC material are also removed.

摘要翻译： 提供了一种用于创建双镶嵌结构的互连图案的新方法。 双镶嵌结构在两个相邻的电介质层上产生，第一蚀刻停止层沉积在衬底的表面上，第二蚀刻停止层沉积在两层介电层之间。 第一蚀刻穿透两层电介质，第二蚀刻穿透顶部电介质层。 在执行第二蚀刻之前，沉积ARC层。 对于第二蚀刻，使用聚合物富集的蚀刻剂来保护开口的侧壁。 第二蚀刻留下了通过下电介质的开口周围形成的材料（含有C，H，F和氧化物化合物）的栅栏。 该栅栏保护双镶嵌结构的下开口的上角，并以两步程序移除。 在完成这个两步骤程序后，双镶嵌结构的下开口的上角保留了矩形轮廓。 最后一步从电介质的第二层的表面去除光致抗蚀剂（已用于形成互连线开口），而ARC材料的残余物也被去除。

公开(公告)号：US06194128B1

公开(公告)日：2001-02-27

申请号：US09156053

申请日：1998-09-17

申请人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

IPC分类号： G03F700

CPC分类号： H01L21/76835 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L2221/1036

摘要： A novel method of dual damascene etching is disclosed. It is shown that the performance of ULSI circuits can be improved by shrinking interconnect dimensions through the use of dual damascene processes, using hard-masks to achieve vertical walls and hence smaller spaces in the damascene structures, introducing low-k (dielectric constant) insulating materials to reduce RC delays, and metallizing with copper without the deleterious effects of bridging after CMP. These are accomplished by using a novel recipe for etching the hard-masks used in a dual damascene process and still another recipe for etching low-k dielectric layers in three different combinations with oxide-based dielectric layers.

摘要翻译： 公开了一种双镶嵌蚀刻的新方法。 通过使用双镶嵌工艺，通过使用硬掩模实现垂直壁并因此在镶嵌结构中实现更小的空间来缩小互连尺寸，可以提高ULSI电路的性能，引入低k（介电常数）绝缘 减少RC延迟的材料，以及铜的金属化，而没有CMP后的桥接的有害影响。 这些是通过使用用于蚀刻在双镶嵌工艺中使用的硬掩模的新配方来实现的，还有另一种用于蚀刻具有氧化物基电介质层的三种不同组合的低k电介质层的方案。

公开(公告)号：US06183937B2

公开(公告)日：2001-02-06

申请号：US09072997

申请日：1998-05-06

申请人： Chia-Shiung Tsai ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Hun-Jan Tao

IPC分类号： G03F700

CPC分类号： G03F7/2024 ,  G03F7/0045 ,  G03F7/40

摘要： A method for forming a patterned photoresist layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer having a first linewidth. There is then irradiated isotropically the patterned photoresist layer with an isotropic radiation source to decompose a conformal surface layer of the patterned photoresist layer while simultaneously forming a conformal surface layer decomposed patterned photoresist layer having a second linewidth narrower than first linewidth. The conformal surface layer decomposed patterned photoresist layer may then be employed as an etch mask layer when etching a blanket microelectronics layer formed interposed between the substrate and the conformal surface layer decomposed patterned photoresist layer. Through the method there may be formed a patterned microelectronics layer of narrow linewidth without employing an advanced photoexposure apparatus.

摘要翻译： 一种形成图案化光致抗蚀剂层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成覆盖光致抗蚀剂层。 然后照射曝光并显影覆盖光致抗蚀剂层以形成具有第一线宽的图案化光致抗蚀剂层。 然后将具有各向同性辐射源的图案化光致抗蚀剂层各向同性地照射，以分解图案化光致抗蚀剂层的共形表面层，同时形成具有比第一线宽窄的第二线宽的共形表面层分解的图案化光致抗蚀剂层。 然后当蚀刻形成在介于基底和保形表面层分解的图案化光致抗蚀剂层之间的覆盖微电子层时，共形表面层分解的图案化光致抗蚀剂层可用作蚀刻掩模层。 通过该方法，可以形成窄线宽的图案化微电子学层，而不使用先进的曝光装置。

公开(公告)号：US06174818B1

公开(公告)日：2001-01-16

申请号：US09443424

申请日：1999-11-19

申请人： Hun-Jan Tao ,  Huan-Just Lin ,  Hung-Chang Hsieh ,  Chu-Yun Fu ,  Ying-Ying Wang ,  Chia-Shiung Tsai ,  Fang-Cheng Chen

发明人： Hun-Jan Tao ,  Huan-Just Lin ,  Hung-Chang Hsieh ,  Chu-Yun Fu ,  Ying-Ying Wang ,  Chia-Shiung Tsai ,  Fang-Cheng Chen

IPC分类号： H01L21302

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/32139

摘要： A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.

摘要翻译： 描述了用于形成用于FET中的栅电极的非常窄的多晶硅栅极线的工艺。 该方法在蚀刻多晶硅期间使用由氧化硅薄层覆盖的氮氧化硅的消耗性硬掩模。 选择构成硬掩模的两层的厚度，使得该结构也用作其上方的光致抗蚀剂涂层的ARC。 为了提高分辨率，使用后者的较薄层。 在光致抗蚀剂被图案化之后，可以对其进行修整或者可以将其去除并重新形成，因为氧化硅层为下面的氮氧化硅提供保护。 在形成硬掩模之后，除去所有光致抗蚀剂并蚀刻多晶硅。 在蚀刻期间，同时去除氧化硅层和部分氮氧化硅。

公开(公告)号：US5899748A

公开(公告)日：1999-05-04

申请号：US859863

申请日：1997-05-21

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76802 ,  H01L21/76814

摘要： The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process. The hydrogen ions generated combines with the fluorine contained in the oxide forming HF for etching away the interface between the two different oxide layers where boron ions and phosphorous ions are saturated at such interfaces.

摘要翻译： 本发明公开了一种用于通过利用BPTEOS氧化物和TEOS氧化物的交替层和深UV光致抗蚀剂来固定通孔/接触或形成具有增加的电容的电容器的noel方法，从而可以形成环形空腔 在通过等离子体蚀刻工艺形成通孔/接触开口或电容器开口期间在BPTEOS氧化物层和TEOS氧化物层之间的界面处。 可以通过沉积在半导体结构上的BPTEOS氧化物层的数量来适当地调节形成的空腔数量，即在通孔/接触器或电容器上形成的锚定件的数量。 每个BPTEOS氧化物层在通孔/触点或电容器上产生两个锚点。 深UV光致抗蚀剂层应含有光酸发生剂，使得当光致抗蚀剂层经受紫外线辐射和加热氢离子产生过程时，发射氢离子。 产生的氢离子与形成HF的氧化物中所含的氟组合，用于蚀刻掉在这些界面处硼离子和磷离子饱和的两个不同氧化物层之间的界面。

公开(公告)号：US5871658A

公开(公告)日：1999-02-16

申请号：US782708

申请日：1997-01-13

申请人： Hun-Jan Tao ,  Chia Shiung Tsai ,  Chen-Hua Yu

发明人： Hun-Jan Tao ,  Chia Shiung Tsai ,  Chen-Hua Yu

IPC分类号： H01L21/66 ,  H01L21/00

CPC分类号： B24B37/013 ,  H01L22/26

摘要： A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer. While etching through the plasma etch method there is adjusted at least one of a first control parameter which controls the first plasma etchant component concentration and a second control parameter which controls the second plasma etchant component concentration to provide through the plasma etch method from the blanket layer a patterned layer with a pre-determined blanket layer to patterned photoresist layer plasma etch selectivity. There is also disclosed an apparatus through which the method may be practiced.

摘要翻译： 一种用于监测和控制用于形成图案化层的等离子体蚀刻方法的方法。 首先提供了具有在其上形成的覆盖层的衬底，所述覆盖层具有在其上形成的图案化的光致抗蚀剂层。 然后通过等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为图案化的光致抗蚀剂蚀刻掩模层来形成图案层。 等离子体蚀刻方法是通过光学发射光谱法（OES）监测的，该方法监测与第一等离子体蚀刻剂成分有关的最小值，该第一等离子体蚀刻剂成分涉及橡皮布层的化学蚀刻和第二等离子体蚀刻剂部件，其涉及物理溅射蚀刻 覆盖层和图案化的光致抗蚀剂层。 在蚀刻通过等离子体蚀刻方法时，调节控制第一等离子体蚀刻剂成分浓度的第一控制参数和控制第二等离子体蚀刻剂成分浓度的第二控制参数中的至少一个，以通过等离子体蚀刻方法从覆盖层 具有预定覆盖层的图案化层到图案化的光致抗蚀剂层等离子体蚀刻选择性。 还公开了可以实施该方法的装置。

公开(公告)号：US20050158666A1

公开(公告)日：2005-07-21

申请号：US11037787

申请日：2005-01-18

申请人： Jen-Cheng Liu ,  Shu-Chih Yang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Jen-Cheng Liu ,  Shu-Chih Yang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： G03C5/00 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138

摘要： A method for etching a pattern within a dual-layer stack dielectric layer employed within a microelectronics fabrication. A first low dielectric constant dielectric layer employing HSQ polymer spin-on-glass (SOP) dielectric material is formed over a substrate. A second dielectric layer is then provided to form a dual level dielectric stack layer. There is then formed over the dual dielectric layer a patterned photoresist etch mask layer. The pattern is transferred into and through the dielectric stack layer employing an anisotropic reactive ion etching environment to etch the pattern through the patterned photoresist etch mask layer. There is then added to the etchant environment additional gases under conditions to form a plasma in the final etching environment to stabilize the etched pattern surface and attenuate degradation of the etched pattern during subsequent stripping of the photoresist etch mask pattern.

摘要翻译： 一种用于蚀刻在微电子制造中采用的双层堆叠介质层内的图案的方法。 在衬底上形成采用HSQ聚合物旋涂玻璃（SOP）电介质材料的第一低介电常数介电层。 然后提供第二电介质层以形成双电平电介质堆叠层。 然后在双电介质层上形成图案化的光致抗蚀剂蚀刻掩模层。 使用各向异性反应离子蚀刻环境将图案转移到介电堆叠层中并通过电介质堆叠层，以通过图案化的光致抗蚀剂蚀刻掩模层蚀刻图案。 然后在蚀刻剂环境中添加另外的气体，以在最终蚀刻环境中形成等离子体，以稳定蚀刻图案表面，并在随后剥离光致抗蚀剂蚀刻掩模图案期间减弱蚀刻图案的劣化。

公开(公告)号：US06331480B1

公开(公告)日：2001-12-18

申请号：US09252469

申请日：1999-02-18

申请人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831

摘要： A method for improving the adhesion, between an overlying insulator layer, and an underlying low K layer, used for forming a composite layer, damascene mask pattern, wherein the damascene mask pattern is used as an interlevel dielectric layer, between metal interconnect structures, has been developed. A treatment, comprised of aqueous NH4OH solutions, or of UV curing procedures, is performed on the top surface of the low K layer, prior to deposition of the overlying insulator layer. The treatment, resulting in a roughened top surface of the low K layer, allows removal of masking photoresist shapes, to be aggressively accomplished using wet strippers, without adhesion loss at the insulator—low K layer interface.

摘要翻译： 在金属互连结构之间用于改善用于形成复合层的上覆绝缘体层和下层低K层之间的附着力的方法，其中镶嵌掩模图案用作层间绝缘层，镶嵌掩模图案具有 已经开发 在沉积上层绝缘体层之前，在低K层的顶表面上进行由NH 4 OH水溶液组成或UV固化程序的处理。 导致低K层的粗糙顶表面的处理允许去除掩模光致抗蚀剂形状，使用湿剥离剂积极地实现，而在绝缘体低K层界面处没有粘附损失。

公开(公告)号：US06319822B1

公开(公告)日：2001-11-20

申请号：US09164999

申请日：1998-10-01

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。