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218 条记录 (耗时 0.039 秒)

    Process for forming an integrated contact or via
    1.
    发明授权
    Process for forming an integrated contact or via 有权
    用于形成集成接触或通孔的工艺

    公开(公告)号：US06319822B1

    公开(公告)日：2001-11-20

    申请号：US09164999

    申请日：1998-10-01

    申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

    发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

    IPC分类号： H01L214763

    CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

    摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

    摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

    Method for forming a multi-anchor DRAM capacitor and capacitor formed
    2.
    发明授权
    Method for forming a multi-anchor DRAM capacitor and capacitor formed 失效
    形成多锚式DRAM电容器和电容器的方法

    公开(公告)号：US6015735A

    公开(公告)日：2000-01-18

    申请号：US6509

    申请日：1998-01-13

    申请人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

    发明人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/302

    CPC分类号： H01L27/1085 ,  H01L28/86

    摘要： The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

    摘要翻译： 本发明公开了一种用于形成DRAM电容器的方法，该DRAM电容器通过利用首先沉积掺杂和未掺杂电介质材料的交替层的沉积工艺具有改善的电荷存储容量，然后将深UV型光致抗蚀剂层沉积在氧化物层的顶部 使得在用于电池开口的高密度等离子体蚀刻工艺期间，当在蚀刻室中暴露于UV发射时，光致抗蚀剂层产生酸性反应产物，使得电池开口的侧壁以不均匀的方式横向蚀刻，即， 掺杂的介电层比非掺杂的介电层更严格地被蚀刻，从而形成额外的表面积和改善的形成的电容器的电荷存储容量。

    Fluorine-doped silicate glass hard mask to improve metal line etching profile
    3.
    发明授权
    Fluorine-doped silicate glass hard mask to improve metal line etching profile 失效

    公开(公告)号：US5962346A

    公开(公告)日：1999-10-05

    申请号：US998673

    申请日：1997-12-29

    申请人： Shau-Lin Shue ,  Chia-Shiung Tsai

    发明人： Shau-Lin Shue ,  Chia-Shiung Tsai

    IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/443

    CPC分类号： H01L21/02071 ,  H01L21/32139 ,  Y10S438/945

    摘要： A new method of etching metal lines using fluorine-doped silicate glass as a hard mask is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A metal layer is deposited overlying the insulating layer. A layer of fluorine-doped silicate glass is deposited overlying the metal layer wherein the fluorine-doped silicate glass layer acts as a hard mask. The hard mask is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer not covered by the patterned hard mask is etched away to form metal lines whereby fluorine ions released from the patterned hard mask form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit is completed.

    Fluorine-doped silicate glass hard mask to improve metal line etching profile
    4.
    发明授权
    Fluorine-doped silicate glass hard mask to improve metal line etching profile 有权
    氟掺杂硅酸盐玻璃硬掩模，以改善金属线蚀刻轮廓

    公开(公告)号：US06417569B1

    公开(公告)日：2002-07-09

    申请号：US09378499

    申请日：1999-08-20

    申请人： Shau-Lin Shue ,  Chia-Shiung Tsai

    发明人： Shau-Lin Shue ,  Chia-Shiung Tsai

    IPC分类号： H01L2348

    CPC分类号： H01L21/32139

    摘要： A new method of etching metal lines using fluorine-doped silicate glass as a hard mask is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A metal layer is deposited overlying the insulating layer. A layer of fluorine-doped silicate glass is deposited overlying the metal layer wherein the fluorine-doped silicate glass layer acts as a hard mask. The hard mask is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer not covered by the patterned hard mask is etched away to form metal lines whereby fluorine ions released from the patterned hard mask form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit is completed.

    摘要翻译： 描述了使用掺氟硅酸盐玻璃作为硬掩模蚀刻金属线的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 沉积在绝缘层上的金属层。 一层氟掺杂的硅酸盐玻璃沉积在金属层上，其中氟掺杂的硅酸盐玻璃层用作硬掩模。 硬掩模被一层光致抗蚀剂覆盖。 光致抗蚀剂层暴露于光化光，并显影并图案化以形成所需的光致抗蚀剂掩模。 硬掩模被蚀刻掉，其未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 被图案化的硬掩模未被覆盖的金属层被蚀刻掉以形成金属线，由此从图案化的硬掩模释放的氟离子在金属线的侧壁上形成钝化层，从而防止金属线的底切，导致金属线具有 垂直剖面。 去除光致抗蚀剂掩模并完成集成电路的制造。

    Method for thinning a wafer
    9.
    发明授权
    Method for thinning a wafer 有权
    减薄晶片的方法

    公开(公告)号：US08252682B2

    公开(公告)日：2012-08-28

    申请号：US12704695

    申请日：2010-02-12

    申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

    发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

    IPC分类号： H01L21/44 ,  H01L23/48

    CPC分类号： H01L21/76898 ,  H01L2224/02372

    摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

    摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。