公开(公告)号：US06319822B1

公开(公告)日：2001-11-20

申请号：US09164999

申请日：1998-10-01

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

申请人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC分类号： H01L21/31138 ,  H01L21/76802

摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

摘要翻译： 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US6025273A

公开(公告)日：2000-02-15

申请号：US55433

申请日：1998-04-06

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L2924/0002

摘要： A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.

摘要翻译： 实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。 该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。 这提供了使接触孔宽度小于0.25μm的非常理想的方法。 在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。 光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。 去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。 这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。 硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。 现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

公开(公告)号：US5981398A

公开(公告)日：1999-11-09

申请号：US58122

申请日：1998-04-10

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/3065

CPC分类号： H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.

摘要翻译： 一种形成含氯等离子体蚀刻图案层的方法。 首先提供了在微电子制造中使用的衬底10。 然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。 然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。 然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时， 以形成图案化的硬掩模层。 最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

公开(公告)号：US06194128B1

公开(公告)日：2001-02-27

申请号：US09156053

申请日：1998-09-17

申请人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

IPC分类号： G03F700

CPC分类号： H01L21/76835 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L2221/1036

摘要： A novel method of dual damascene etching is disclosed. It is shown that the performance of ULSI circuits can be improved by shrinking interconnect dimensions through the use of dual damascene processes, using hard-masks to achieve vertical walls and hence smaller spaces in the damascene structures, introducing low-k (dielectric constant) insulating materials to reduce RC delays, and metallizing with copper without the deleterious effects of bridging after CMP. These are accomplished by using a novel recipe for etching the hard-masks used in a dual damascene process and still another recipe for etching low-k dielectric layers in three different combinations with oxide-based dielectric layers.

摘要翻译： 公开了一种双镶嵌蚀刻的新方法。 通过使用双镶嵌工艺，通过使用硬掩模实现垂直壁并因此在镶嵌结构中实现更小的空间来缩小互连尺寸，可以提高ULSI电路的性能，引入低k（介电常数）绝缘 减少RC延迟的材料，以及铜的金属化，而没有CMP后的桥接的有害影响。 这些是通过使用用于蚀刻在双镶嵌工艺中使用的硬掩模的新配方来实现的，还有另一种用于蚀刻具有氧化物基电介质层的三种不同组合的低k电介质层的方案。

公开(公告)号：US6043163A

公开(公告)日：2000-03-28

申请号：US999233

申请日：1997-12-29

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/32136

摘要： A new method of etching metal lines using HCl in the overetch step to prevent undercutting of the metal lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A hard mask layer is deposited overlying the metal layer. The hard mask layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The hard mask layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form the metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein HCl gas is one of the etchant gases used in the overetching whereby hydrogen ions from the HCl gas react with the metal layer and the barrier metal layer to form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在过蚀刻步骤中使用HCl蚀刻金属线以防止金属线的底切的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 覆盖在绝缘层上的阻挡金属层被沉积​​。 沉积在阻挡金属层上的金属层。 覆盖金属层的硬掩模层被沉积。 硬掩模层被一层光致抗蚀剂覆盖，该层被曝光，显影和图案化以形成所需的光致抗蚀剂掩模。 将硬掩模层蚀刻掉，其中未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 金属层被蚀刻掉，其中未被图案化的硬掩模覆盖以形成金属线。 进行过蚀刻以去除其未被硬掩模覆盖的阻挡层，其中HCl气体是用于过蚀刻中的蚀刻剂气体之一，其中来自HCl气体的氢离子与金属层和阻挡金属层反应形成 钝化层，从而防止金属线的底切，导致具有垂直轮廓的金属线。 去除光致抗蚀剂掩模并完成集成电路器件的制造。

公开(公告)号：US06383943B1

公开(公告)日：2002-05-07

申请号：US09687160

申请日：2000-10-16

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

IPC分类号： H01L21302

CPC分类号： H01L21/76843 ,  H01L21/3105 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.

摘要翻译： 一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。 图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。 金属间电介质（IMD）层然后覆盖整个表面。 进行各向异性蚀刻，留下IMD层中的通孔。 然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。 本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。 执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。 粘合层适用于衬套通孔。 然后沉积第二导电层并且将表面平坦化。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US5994229A

公开(公告)日：1999-11-30

申请号：US5567

申请日：1998-01-12

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai

IPC分类号： H01L21/3065 ,  H01L21/762

CPC分类号： H01L21/3065 ,  H01L21/76232

摘要： A process for forming a shallow trench having steep sidewalls near its bottom and sloping sidewalls at the top is described. The process is in 3 stages. The first stage involves methane trifluoride, carbon tetrafluoride, argon, and oxygen. The second stage involves methane trifluoride and methane monofluoride, while the third stage involves hydrogen bromide, chlorine, and helium/oxygen. If the ratio of the various components at each stage is carefully controlled along with other variables such as discharge power, pressure, and duration, the trench profile described above is obtained with a minimum of deposited polymer material on the sidewalls.

摘要翻译： 描述了一种用于形成在其底部附近具有陡峭侧壁并且在顶部具有倾斜侧壁的浅沟槽的工艺。 这个过程分3个阶段。 第一阶段涉及三氟化甲烷，四氟化碳，氩气和氧气。 第二阶段涉及甲烷三氟化氢和甲烷单氟化物，而第三阶段涉及溴化氢，氯气和氦气/氧气。 如果每个阶段的各种组分的比例与诸如放电功率，压力和持续时间的其他变量一起被仔细地控制，则上述的沟槽轮廓是通过在侧壁上沉积的最少的聚合物材料获得的。

公开(公告)号：US06309962B1

公开(公告)日：2001-10-30

申请号：US09396516

申请日：1999-09-15

申请人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/76813

摘要： A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.

摘要翻译： 描述了在电介质，特别是低k有机电介质中形成双镶嵌腔的工艺。 电介质由两层由蚀刻停止层隔开组成。 通过使用由两层氧氮化硅分离的氧化硅层组成的硬掩模来实现镶嵌腔的形成。 对于沟槽第一和通过第一方法，仅使用上部氧氮化硅层作为掩模形成第一腔体。 因此，当第二部分被图案化时，由于所述上层相对较薄，所以几乎不发生不对准。 另外的蚀刻步骤导致空腔和沟槽部分延伸到位于电介质层之间的蚀刻停止层的尽可能深。 光致抗蚀剂的最终去除是在硬掩模仍然存在的情况下发生的，因此不会损害有机电介质。 最终蚀刻步骤然后完成该过程。