公开(公告)号：US08254453B2

公开(公告)日：2012-08-28

申请号：US12690921

申请日：2010-01-20

Applicant: Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

Inventor： Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

IPC: H04N7/12 ,  H04N7/26

CPC classification number: H04N19/42 ,  H04N19/12 ,  H04N19/44 ,  H04N19/46 ,  H04N19/593

Abstract: A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.

Abstract translation: 多格式视频解码器包括比特流缓冲器，系统控制器，比特流解码单元，帧内模式解码单元和共享预测模块。 系统控制器根据视频比特流选择性地产生第一控制信号或第二控制信号。 比特流解码单元在接收到第一控制信号时根据视频比特流生成解码信息信号。 帧内模式解码单元在接收到第二控制信号时产生帧内模式信号。 共享预测模块对视频比特流的当前块执行AC / DC预测，根据解码信息信号产生当前第一预测结果，并根据当前块执行帧内预测，​​根据该预测结果生成当前第二预测结果 帧内模式信号。 共享预测模块包括在AC / DC预测和帧内预测中使用的共享组件。

公开(公告)号：US08094712B2

公开(公告)日：2012-01-10

申请号：US12058765

申请日：2008-03-31

Applicant: Chan-Shih Lin ,  Shao-Yung Su

Inventor： Chan-Shih Lin ,  Shao-Yung Su

IPC: H04N11/02

CPC classification number: H04N21/435 ,  H04N21/234327 ,  H04N21/235 ,  H04N21/4331 ,  H04N21/4345 ,  H04N21/84 ,  H04N21/8456

Abstract: An apparatus for processing a data stream having a hierarchical layer structure and including encoded data sets and raw data sets is provided. The apparatus includes a first processing circuit for generating an enable signal corresponding to a predetermined layer of the hierarchical layer structure when detecting that a data set of the data stream corresponds to the predetermined layer, and a second processing circuit coupled to the first processing circuit for detecting whether an identifier of the data set corresponds to one predetermined raw data set identifier when receiving the enable signal from the first processing circuit.

Abstract translation: 提供了一种用于处理具有分层结构并包括编码数据集和原始数据集的数据流的装置。 该装置包括第一处理电路，用于当检测到数据流的数据集对应于预定层时，产生对应于分级层结构的预定层的使能信号;以及第二处理电路，耦合到第一处理电路 当从第一处理电路接收到使能信号时，检测数据集的标识符是否对应于一个预定的原始数据集标识符。

公开(公告)号：US20110182348A1

公开(公告)日：2011-07-28

申请号：US12693445

申请日：2010-01-26

Applicant: Chien-Chang Lin ,  Chan-Shih Lin

Inventor： Chien-Chang Lin ,  Chan-Shih Lin

IPC: H04N11/04 ,  G06F12/08

CPC classification number: H04N19/433 ,  H04N19/44 ,  H04N19/61

Abstract: Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

Abstract translation: 存储在外部存储器中的帧数据被划分为多个宏块，并且提供了包括至少一个宏块的多个存取单元。 通过以预定顺序加载多个访问单元，从外部存储器取出多个帧。 用于解码第一存取单元的宏块的当前数据和用于解码第二存取单元的宏块的参考数据从第一存取单元加载，分别映射到循环缓存的第一存储组和第二存储组 根据帧宽度。

公开(公告)号：US20100226442A1

公开(公告)日：2010-09-09

申请号：US12399525

申请日：2009-03-06

Applicant: Chan-Shih Lin ,  Yin-Her Su

Inventor： Chan-Shih Lin ,  Yin-Her Su

IPC: H04N7/26

CPC classification number: H04N19/423 ,  H04N19/44 ,  H04N19/61

Abstract: A bit-stream buffer controller for a video decoder includes a first FIFO, a second FIFO, and an interrupt controller. The first FIFO is configured to store an input bit-stream. The second FIFO is configured to store a payload extracted from the input bit-stream. The interrupt controller is configured to generate an interrupt signal according to a fullness status of the first FIFO and the second FIFO such that the video decoder may be switched to load the payload without checking the fullness status each time the payload is loaded.

Abstract translation: 用于视频解码器的比特流缓冲器控制器包括第一FIFO，第二FIFO和中断控制器。 第一个FIFO被配置为存储输入比特流。 第二FIFO被配置为存储从输入比特流提取的有效载荷。 所述中断控制器被配置为根据所述第一FIFO和所述第二FIFO的丰满状态产生中断信号，使得所述视频解码器可以在每次所述有效负载被加载时检查所述有效负载而不检查所述充满状态。

公开(公告)号：US07246298B2

公开(公告)日：2007-07-17

申请号：US10990929

申请日：2004-11-17

Applicant: Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

Inventor： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

Abstract: A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

Abstract translation: 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。

公开(公告)号：US20050149838A1

公开(公告)日：2005-07-07

申请号：US10990929

申请日：2004-11-17

Applicant: Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

Inventor： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC: H03M13/03 ,  H03M13/29 ,  H03M13/41

CPC classification number: H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

Abstract: A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

Abstract translation: 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。