公开(公告)号：US07246298B2

公开(公告)日：2007-07-17

申请号：US10990929

申请日：2004-11-17

申请人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

发明人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

摘要： A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

摘要翻译： 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。

公开(公告)号：US20050149838A1

公开(公告)日：2005-07-07

申请号：US10990929

申请日：2004-11-17

申请人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

发明人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC分类号： H03M13/03 ,  H03M13/29 ,  H03M13/41

CPC分类号： H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

摘要： A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

摘要翻译： 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。

公开(公告)号：US08305251B2

公开(公告)日：2012-11-06

申请号：US12702792

申请日：2010-02-09

申请人： Tzi-Dar Chiueh

发明人： Tzi-Dar Chiueh

IPC分类号： H04L17/02

CPC分类号： G08C23/02

摘要： A wireless remote control system is provided. This system includes a remote controller, plural detectors, and a decision module. The detectors are used for detecting the frequency a wireless signal emitted by the remote controller and respectively generate a detecting result. Based on at least one frequency difference between the detecting results, the decision module determines how the remote controller is moving and thereby generates a control signal. Because the decision module needs no knowledge of the frequency of the emitted wireless signal, the wireless remote controller has the advantages of small size, low cost, and low power consumption.

摘要翻译： 提供无线遥控系统。 该系统包括遥控器，多个检测器和决定模块。 检测器用于检测由遥控器发射的无线信号的频率，并分别产生检测结果。 基于检测结果之间的至少一个频率差，决定模块确定遥控器如何移动，从而产生控制信号。 由于决策模块不需要了解发射无线信号的频率，所以无线遥控器具有体积小，成本低，功耗低的优点。

公开(公告)号：US06674824B1

公开(公告)日：2004-01-06

申请号：US09339704

申请日：1999-06-24

申请人： Tzi-Dar Chiueh ,  Jen-Shi Wu ,  Jin-Bin Yang

发明人： Tzi-Dar Chiueh ,  Jen-Shi Wu ,  Jin-Bin Yang

IPC分类号： H04D324

CPC分类号： H03L7/187 ,  H03K3/0322 ,  H03L7/089 ,  H03L7/0995 ,  H03L7/10 ,  H03L7/193

摘要： A mixed-signal-controlled phase-locked loop is provided. This loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, a phase-frequency detector circuit electrically connected to the mixed-signal-controlled oscillator circuit, detecting the phase and the oscillating frequency of the oscillating signal and comparing the phase and the oscillating frequency with those of a reference signal to generate an error signal after the phase and oscillating frequency are detected, and a mixed-control-signal-producing circuit electrically connected to the mixed-signal-controlled oscillator circuit and the phase-frequency detector circuit for receiving the error signal to output the analog control signal and the digital control signal to the mixed-signal-controlled oscillator circuit.

摘要翻译： 提供了混合信号控制的锁相环。 该回路包括混合信号控制振荡器电路，用于响应于数字控制信号和模拟控制信号产生具有振荡频率和相位的振荡信号，相位频率检测器电路电连接到混合信号 - 控制振荡电路，检测振荡信号的相位和振荡频率，并将相位和振荡频率与参考信号的相位和振荡频率进行比较，以在检测到相位和振荡频率之后产生误差信号，混合控制信号 电连接到混合信号控制振荡器电路和相位频率检测器电路，用于接收误差信号，以将模拟控制信号和数字控制信号输出到混合信号控制振荡器电路。

公开(公告)号：US5799134A

公开(公告)日：1998-08-25

申请号：US441128

申请日：1995-05-15

申请人： Tzi-Dar Chiueh ,  Hwai-Tsu Chang

发明人： Tzi-Dar Chiueh ,  Hwai-Tsu Chang

IPC分类号： G06N3/063 ,  G06N3/10 ,  G06F15/18

CPC分类号： G06N3/10 ,  G06N3/063

摘要： A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.

摘要翻译： 用于实现神经网络的电路包括由微处理器控制的处理元件的一维收缩阵列。 一维心脏收缩阵列可以实现包括具有各种不同激活功能的神经元的加权和径向型网络。 流水线处理和分区用于优化收缩阵列中的数据流。 因此，本发明的电路可以以非常有效的方式实现各种神经网络。

公开(公告)号：US08692550B2

公开(公告)日：2014-04-08

申请号：US13050715

申请日：2011-03-17

申请人： Jyh-Horng Chen ,  Tzi-Dar Chiueh ,  Edzer L. Wu

发明人： Jyh-Horng Chen ,  Tzi-Dar Chiueh ,  Edzer L. Wu

IPC分类号： G01R33/44 ,  G01R33/483

CPC分类号： G01R33/4835

摘要： A method for acquiring MRI signals includes: applying one or more than one RF pulse, which carries at least two frequency components, and a slice/slab selection gradient to a subject, so that at least two slices/slabs of the subject respectively corresponding to the at least two frequency components are excited simultaneously; applying a plurality of spatial encoding gradients; applying a plurality of separation gradients for separating the at least two slices/slabs; and applying at least one coherent refocusing gradient between the plurality of separation gradients.

摘要翻译： 一种用于获取MRI信号的方法包括：将一个或多于一个的RF脉冲（其携带至少两个频率分量）和切片/平板选择梯度施加到对象，使得被摄体的至少两个切片/平板分别对应于 同时激励至少两个频率分量; 应用多个空间编码梯度; 施加多个用于分离所述至少两个切片/平板的分离梯度; 以及在所述多个分离梯度之间施加至少一个相干重聚焦梯度。

公开(公告)号：US20110254550A1

公开(公告)日：2011-10-20

申请号：US13088557

申请日：2011-04-18

申请人： Jyh-Horng Chen ,  Tzi-Dar Chiueh ,  Edzer L. Wu

发明人： Jyh-Horng Chen ,  Tzi-Dar Chiueh ,  Edzer L. Wu

IPC分类号： G01R33/48

CPC分类号： G01R33/56341 ,  G01N24/08 ,  G01R33/446 ,  G01R33/4828 ,  G01R33/4835 ,  G01R33/543

摘要： A diffusion imaging method is provided. The diffusion imaging method includes performing a plurality of data collection sequences. Each data collection sequence includes applying an excitation radio frequency signal and a selection gradient. The excitation radio frequency signal includes a first set of frequency bands selected to simultaneously excite a first nuclei type in a plurality of cross sections of a subject. Each data collection sequence further includes applying a diffusion gradient during formation of a magnetic resonance signal, applying a spatial encoding gradient during formation of the magnetic resonance signal, and while acquiring the magnetic resonance signal, applying a separation gradient to change a frequency separation between portions of the magnetic resonance signal. The diffusion imaging method further includes computationally determining a diffusion image of each of the plurality of cross sections.

摘要翻译： 提供扩散成像方法。 扩散成像方法包括执行多个数据收集序列。 每个数据收集序列包括施加激发射频信号和选择梯度。 激励射频信号包括被选择以同时激发被摄体的多个横截面中的第一核型的第一组频带。 每个数据收集序列还包括在形成磁共振信号期间施加扩散梯度，在形成磁共振信号期间施加空间编码梯度，并且在获取磁共振信号的同时，施加分离梯度以改变部分之间的频率间隔 的磁共振信号。 扩散成像方法还包括计算确定多个横截面中的每一个的扩散图像。

公开(公告)号：US20170089609A1

公开(公告)日：2017-03-30

申请号：US15059356

申请日：2016-03-03

申请人： Tzi-Dar Chiueh ,  Chun-Ming Huang ,  Chen-Chia Chen ,  Chien-Ming Wu

发明人： Tzi-Dar Chiueh ,  Chun-Ming Huang ,  Chen-Chia Chen ,  Chien-Ming Wu

IPC分类号： F24H9/20 ,  F23Q3/00

CPC分类号： F24H9/2035 ,  F23N2027/28 ,  F23N2031/02 ,  F23N2041/04 ,  F23Q3/008

摘要： The ignition system includes a mini hydroelectric generator module connecting an inlet pipe for generating electricity by water flow passing through the inlet pipe and it; a power quality monitoring module electrically connecting the mini hydroelectric generator module for monitoring output electricity quality of the mini hydroelectric generator module and switching on/off the electricity; an ignitor electrically connecting the power quality monitoring module for receiving electricity from the power quality monitoring module to ignite; and an electronic valve electrically connecting the power quality monitoring module for receiving electricity from the power quality monitoring module to switch on/off a gas pipe.

公开(公告)号：US07277479B2

公开(公告)日：2007-10-02

申请号：US10248920

申请日：2003-03-02

申请人： Tzi-Dar Chiueh ,  Kuan-Hung Chen

发明人： Tzi-Dar Chiueh ,  Kuan-Hung Chen

IPC分类号： H03K7/00 ,  G06F17/10

CPC分类号： H03H17/0294

摘要： A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.

摘要翻译： 一系列数字处理单元（DPU）被连接以形成有限脉冲响应（FIR）滤波器。 每个DPU包括寄存器，多路复用器和系数乘法器。 寄存器存储并延迟要过滤的输入数字信号。 多路复用器具有连接到输入节点和寄存器的输出的输入，多路复用器的输出用于连接到下一级DPU。 系数乘法器连接到寄存器的输出，并将输入信号乘以系数或系数的一部分。 一组DPU可以设置多路复用器，使得每个DPU的寄存器存储用于处理单个滤波器系数的输入信号的相同部分。 提供加法器以对DPU的输出进行求和并输出滤波信号。 FIR滤波器的关键路径与系数数和精度无关。

公开(公告)号：US07170800B2

公开(公告)日：2007-01-30

申请号：US11124999

申请日：2005-05-09

申请人： Tzi-Dar Chiueh ,  Po-Chun Hsieh

发明人： Tzi-Dar Chiueh ,  Po-Chun Hsieh

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G06F5/10 ,  G06F2205/104 ,  G11C7/22 ,  G11C8/04 ,  G11C19/00

摘要： A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

摘要翻译： 提供了一种低功率延迟缓冲电路，其利用环形计数器作为地址解码器和用于存储器的锁存器阵列。 为了降低功耗，门控时钟驱动树被应用于环计数器寻址架构。 此外，类似的门控驱动器树被应用于锁存器阵列的输入和输出端口。 延迟缓冲电路不仅可以实现低于基于SRAM的延迟缓冲器的功耗，而且可以在高频下运行，并且占用比基于SRAM的延迟缓冲器更少的布局面积。