公开(公告)号：US5253209A

公开(公告)日：1993-10-12

申请号：US736468

申请日：1991-07-26

申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans D. Oberle

发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans D. Oberle

IPC分类号： G11C11/401 ,  G01R31/28 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/18 ,  G11C29/34

CPC分类号： G11C29/18 ,  G11C11/4094 ,  G11C11/4096

摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

摘要翻译： 集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。 内部加权电路各自分配给内部位线对中的相应一个。 外部一对位线通常被分配给内部位线。 分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。 位线解码器触发分离晶体管对。 提供外部加权电路。 鉴别器装置和预充电装置连接到外部位线对。 每对内部位线的内部位线彼此分开触发。 每对内部位线的内部位线彼此分开连接到外部位线对。

公开(公告)号：US06392918B2

公开(公告)日：2002-05-21

申请号：US09817578

申请日：2001-03-26

申请人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

发明人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

摘要翻译： 用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。 在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。 可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

公开(公告)号：US06452830B2

公开(公告)日：2002-09-17

申请号：US09767805

申请日：2001-01-22

申请人： Oskar Kowarik ,  Kurt Hoffmann

发明人： Oskar Kowarik ,  Kurt Hoffmann

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first and a second electrode. The first electrode is supplied with a fixed cell plate voltage, the second electrode is connected to the given zone of the first conductivity type. A source and a drain of a MOS transistor are supplied with the fixed cell plate voltage. The channel of the MOS transistor has a channel length extending over at least two of the memory cells. The given zone of the first conductivity type is connected, via a resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.

摘要翻译： 存储器配置包括多个电阻式铁电存储单元。 每个存储单元包括选择晶体管和存储电容器。 选择晶体管具有第一导电类型的给定区域。 存储电容器具有第一和第二电极。 第一电极被提供有固定电池板电压，第二电极连接到第一导电类型的给定区域。 MOS晶体管的源极和漏极被提供有固定电池板电压。 MOS晶体管的沟道具有在至少两个存储单元上延伸的沟道长度。 第一导电类型的给定区域经由电阻器连接到MOS晶体管的沟道，使得给定区域经由电阻器和MOS晶体管电连接到存储电容器的第一电极。

公开(公告)号：US5774014A

公开(公告)日：1998-06-30

申请号：US627568

申请日：1996-04-04

申请人： Johannes Stecker ,  Klaus Luther ,  Kurt Hoffmann ,  Oskar Kowarik

发明人： Johannes Stecker ,  Klaus Luther ,  Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G05F3/24 ,  G05F3/26 ,  H03K19/003 ,  H03K19/0185 ,  G05F1/10

CPC分类号： H03K19/00384 ,  G05F3/262

摘要： An integrated buffer circuit includes a first series circuit connected between a first supply potential and a second supply potential (ground). The first series circuit has a voltage-controlled first constant current source, a first field effect transistor having a gate forming an input of the buffer circuit, a circuit node between the first current source and the first field effect transistor forming an output of the buffer circuit, and a first control input for controlling the first current source with a reference potential having a constant potential difference relative to the first supply potential. A second series circuit is connected between the first supply potential and the second supply potential. The second series circuit has a first resistor, a second constant current source furnishing a current being independent of the first supply potential, and a circuit node between the first resistor and the second current source, establishing the reference potential and being connected to the first control input of the first current source.

摘要翻译： 集成缓冲电路包括连接在第一电源电位和第二电源电位（地）之间的第一串联电路。 第一串联电路具有电压控制的第一恒流源，第一场效应晶体管，其栅极形成缓冲电路的输入，第一电流源与第一场效应晶体管之间的电路节点，形成缓冲器的输出 电路和第一控制输入，用于以相对于第一电源电位具有恒定电位差的参考电位来控制第一电流源。 第二串联电路连接在第一电源电位和第二电源电位之间。 第二串联电路具有第一电阻器，提供独立于第一电源电位的电流的第二恒流源，以及第一电阻器和第二电流源之间的电路节点，建立参考电位并连接到第一控制器 输入第一个电流源。

公开(公告)号：US06747891B2

公开(公告)日：2004-06-08

申请号：US10447358

申请日：2003-05-29

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G11C702

CPC分类号： G11C11/16

摘要： A circuit is provided for the non-destructive, self-normalizing reading-out of MRAM memory cells. Accordingly, read currents of a memory cell are normalized by currents that are maintained at a voltage at which the size of these currents is independent of the cell content. The circuit has a simple construction and without great expenditure, permits the normalization of a read signal.

公开(公告)号：US06480044B2

公开(公告)日：2002-11-12

申请号：US09804322

申请日：2001-03-12

申请人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik

发明人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： H03K300

CPC分类号： G11C16/08 ,  G11C8/10

摘要： A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

摘要翻译： 公开了一种半导体电路，其包含集成到第一导电类型的半导体衬底中的驱动电路，并且包括用于切换正和/或零电压电平的正电压开关晶体管和用于切换负和/或零电压电平的负开关晶体管 。 此外，驱动电路包括位于驱动电路上游的控制电路，并且还被配置在连接到衬底电压的半导体衬底中。 驱动电路的负电压开关晶体管被配置在嵌入在半导体衬底中的外部阱中，并且是与第一导电类型相反的第二导电类型，并且外部阱连接到电源电压。

公开(公告)号：US06317356B1

公开(公告)日：2001-11-13

申请号：US09693764

申请日：2000-10-20

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A configuration for self-referencing a ferroelectric memory cell reads out the ferroelectric memory cell successively while a bit line is precharged to two different, opposing voltages. The voltage values read out from the ferroelectric memory cell are temporarily stored respectively in a first and a second capacitor and then fed to an evaluator circuit.

摘要翻译： 用于自参考铁电存储器单元的配置在位线被预充电到两个不同的相对电压的同时连续地读出铁电存储单元。 从铁电存储单元读出的电压值分别临时存储在第一和第二电容器中，然后馈送到评估器电路。

公开(公告)号：US06806550B2

公开(公告)日：2004-10-19

申请号：US10244258

申请日：2002-09-16

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： H01L2900

CPC分类号： H01L27/10897 ,  G11C7/06 ,  G11C11/4091 ,  G11C2207/2227

摘要： An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

摘要翻译： 评估配置具有第一MOS评估阶段，隔离阶段和双极性评估阶段。 隔离级连接在第一MOS评估阶段和双极性评估阶段之间。 隔离阶段将第一个MOS评估阶段与双相评估阶段隔离开来。 评估配置可以可靠地检测非常小的读取信号并且允许高的集成密度。

公开(公告)号：US06404668B2

公开(公告)日：2002-06-11

申请号：US09767807

申请日：2001-01-22

申请人： Oskar Kowarik ,  Kurt Hoffmann

发明人： Oskar Kowarik ,  Kurt Hoffmann

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the resistive ferroelectric memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first electrode and a second electrode. The first electrode is supplied with a fixed cell plate voltage. The second electrode is connected to the given zone of the first conductivity type. A semiconductor body of a second conductivity type opposite the first conductivity type is provided. A line is formed by a highly doped zone of the first conductivity type. The line is supplied with the cell plate voltage. The second electrode of the storage capacitor is connected via the resistor to the line.

摘要翻译： 存储器配置包括多个电阻式铁电存储单元。 每个电阻型铁电存储单元包括选择晶体管和存储电容器。 选择晶体管具有第一导电类型的给定区域。 存储电容器具有第一电极和第二电极。 第一电极被提供有固定的电池板电压。 第二电极连接到第一导电类型的给定区域。 提供了与第一导电类型相反的第二导电类型的半导体本体。 线由第一导电类型的高掺杂区形成。 线路提供了电池板电压。 存储电容器的第二电极通过电阻器连接到线路。

公开(公告)号：US06768667B2

公开(公告)日：2004-07-27

申请号：US10254693

申请日：2002-09-25

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G11C1124

CPC分类号： H01L27/1024 ,  G11C11/404

摘要： A DRAM memory cell having an isolation transistor formed from a bipolar transistor.

摘要翻译： 具有由双极晶体管形成的隔离晶体管的DRAM存储单元。