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    Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces
    12.
    发明授权
    Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces 有权
    使用牺牲层和空隙空间制造绝缘体上半导体（SOI）衬底和半导体器件的方法

    公开(公告)号：US07265031B2

    公开(公告)日：2007-09-04

    申请号：US10972972

    申请日：2004-10-25

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    Double gate MOS transistors
    14.
    发明授权
    Double gate MOS transistors 失效
    双栅MOS晶体管

    公开(公告)号：US06940129B2

    公开(公告)日：2005-09-06

    申请号：US10715664

    申请日：2003-11-18

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654

    摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.

    摘要翻译： 双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。 至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。 半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。 至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。 底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。 至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。 顶栅电极与底栅电极重叠并与晶体管有源区绝缘。 还提供制造这种晶体管的方法。

    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same
    16.
    发明申请
    Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same 有权
    具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法

    公开(公告)号：US20050133789A1

    公开(公告)日：2005-06-23

    申请号：US11011911

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

    摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

    摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。

    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
    18.
    发明授权
    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same 有权
    具有增加的源/漏接触面积的垂直沟道鳍场效应晶体管及其制造方法

    公开(公告)号：US08466511B2

    公开(公告)日：2013-06-18

    申请号：US12613025

    申请日：2009-11-05

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

    Methods of fabricating field effect transistors having multiple stacked channels
    19.
    发明授权
    Methods of fabricating field effect transistors having multiple stacked channels 有权
    制造具有多个堆叠通道的场效应晶体管的方法

    公开(公告)号：US07615429B2

    公开(公告)日：2009-11-10

    申请号：US11948175

    申请日：2007-11-30

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

    摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

    摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 在预活化图案的相对端处，在衬底上形成源极/漏极区域。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。