-
公开(公告)号：US07122778B2
公开(公告)日：2006-10-17
申请号：US11356199
申请日：2006-02-17
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
摘要翻译： 固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。 多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。 像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。 这种布置使颜色串扰最小化。
-
公开(公告)号：US20090231479A1
公开(公告)日：2009-09-17
申请号：US12421948
申请日：2009-04-10
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译： 固态成像器将阵列每列的模拟像素值转换为数字形式。 计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。 纹波计数器与每个相应的列相关联。 在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。 当模拟斜坡等于像素值时，列比较器将计数器元件选通。 计数器内容供给视频输出总线以产生数字视频信号。 附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。 计数器可以使用二进制补码算术。 可以采用附加的缓冲计数器/锁存器阵列。 纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。
-
公开(公告)号：US07129461B2
公开(公告)日：2006-10-31
申请号：US11434666
申请日：2006-05-16
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.
摘要翻译： 固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。 多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。 像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。 这种布置使颜色串扰最小化。
-
公开(公告)号：US20060157644A1
公开(公告)日：2006-07-20
申请号：US11356199
申请日：2006-02-17
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
-
公开(公告)号：US07903159B2
公开(公告)日：2011-03-08
申请号：US12421948
申请日：2009-04-10
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译： 固态成像器将阵列每列的模拟像素值转换为数字形式。 计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。 纹波计数器与每个相应的列相关联。 在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。 当模拟斜坡等于像素值时，列比较器将计数器元件选通。 计数器内容供给视频输出总线以产生数字视频信号。 附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。 计数器可以使用二进制补码算术。 可以采用附加的缓冲计数器/锁存器阵列。 纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。
-
公开(公告)号：US20060202107A1
公开(公告)日：2006-09-14
申请号：US11434666
申请日：2006-05-16
申请人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Michael Joyner , Thomas Poonnen
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.
摘要翻译： 固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。 多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。 像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。 这种布置使颜色串扰最小化。
-
公开(公告)号：US07045758B2
公开(公告)日：2006-05-16
申请号：US11111334
申请日：2005-04-21
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H04N1/03 , H04N1/0308 , H04N1/1933 , H04N1/1934 , H04N5/3692
摘要： A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
摘要翻译： 固态成像系统具有至少一个具有第一和第二系列像素的CMOS成像器，其中一系列的像素相对于另一系列的像素偏移，即交错。 多个成像器可以端对端排列，跨接线连接像素输出导体或每个像素，以便像素馈送到每个系列的公共输出放大器，以最小化芯片到芯片的偏移电压。 像素可以彼此对角地偏移，并且可以构造彩色成像器，其中色带滤光器对角地布置在成像区域上。 这种布置使颜色串扰最小化。
-
公开(公告)号：US20060012696A1
公开(公告)日：2006-01-19
申请号：US11230385
申请日：2005-09-20
申请人： Jeffrey Zarnowski , Ketan Karia , Thomas Poonnen
发明人： Jeffrey Zarnowski , Ketan Karia , Thomas Poonnen
IPC分类号： H04N3/14
CPC分类号： H04N5/335 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/3742 , H04N5/37455 , H04N5/3765 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A ripple counter or equivalent is associated with each respective column. A clock supplies clock signals to the counter elements. A comparator in each column gates the counter element when the analog ramp equals the pixel value for that column. The contents of the counters are transferred sequentially to a video output bus to produce the digital video signal. Additional black-level readout counter elements can create and store a digital value that corresponds to a dark or black video level. A subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer counter/latches can be employed. The ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses for the DAC counter and for the ripple counters can be at the same or different rates.
-
公开(公告)号：US07518646B2
公开(公告)日：2009-04-14
申请号：US11230385
申请日：2005-09-20
CPC分类号： H04N5/335 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/3742 , H04N5/37455 , H04N5/3765 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A ripple counter or equivalent is associated with each respective column. A clock supplies clock signals to the counter elements. A comparator in each column gates the counter element when the analog ramp equals the pixel value for that column. The contents of the counters are transferred sequentially to a video output bus to produce the digital video signal. Additional black-level readout counter elements can create and store a digital value that corresponds to a dark or black video level. A subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer counter/latches can be employed. The ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译： 固态成像器将阵列每列的模拟像素值转换为数字形式。 N位计数器提供N位DAC以产生具有与计数器内容相对应的电平的模拟斜坡输出。 纹波计数器或等效物与每个相应的列相关联。 时钟向计数器元件提供时钟信号。 当模拟斜坡等于该列的像素值时，每列中的比较器对计数器元件进行门控。 计数器的内容被顺序地传送到视频输出总线以产生数字视频信号。 附加的黑电平读出计数器元件可创建并存储对应于暗或黑色视频电平的数字值。 减法元素从像素值中减去黑电平值以减少固定图案噪声。 可以采用附加的缓冲计数器/锁存器阵列。 纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平计时到输出总线。 DAC计数器和纹波计数器的时钟脉冲可以具有相同或不同的速率。
-
公开(公告)号：US20080077647A1
公开(公告)日：2008-03-27
申请号：US11850887
申请日：2007-09-06
申请人： Adly Fam , Thomas Poonnen
发明人： Adly Fam , Thomas Poonnen
IPC分类号： G06F7/487
CPC分类号： G06F7/5324
摘要： Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted forms of the multiplier. The Omega unit may have a plurality of control units, a plurality of switch units, and a multi-shifter-adder (“MSA”). In some embodiments of the invention, more than one Omega unit is provided.
摘要翻译： 公开了二进制数乘法的系统和方法。 在一个这样的系统中有一个Sigma单位和一个欧米茄单位。 Sigma单位可以产生乘数的部分和和乘法器的移位形式。 Omega单元可以具有多个控制单元，多个开关单元和多移位加法器（“MSA”）。 在本发明的一些实施例中，提供了多于一个的Omega单元。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.026 秒)