公开(公告)号：US08309455B2

公开(公告)日：2012-11-13

申请号：US13165522

申请日：2011-06-21

申请人： Sung Jin Kim ,  Alexander Nickel ,  Minh-Van Ngo ,  Hieu Trung Pham ,  Masato Tsuboi ,  Shinich Imada

发明人： Sung Jin Kim ,  Alexander Nickel ,  Minh-Van Ngo ,  Hieu Trung Pham ,  Masato Tsuboi ,  Shinich Imada

IPC分类号： H01L21/4763

CPC分类号： H01L21/3185 ,  H01L21/02074 ,  H01L21/28282 ,  H01L29/792

摘要： Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH4) flow, reducing the overall exposure of the structure to hydrogen radicals. This results in the silicon nitride being strongly bonded to the structure and in improved performance.

摘要翻译： 在结构上沉积氮化硅（SiN）层之前，进行非等离子体增强操作，其中结构暴露于硅烷（SiH 4）流，从而减少了结构对氢自由基的总体暴露。 这导致氮化硅牢固地结合到结构上并且具有改进的性能。

公开(公告)号：US20100230743A1

公开(公告)日：2010-09-16

申请号：US12788177

申请日：2010-05-26

申请人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

发明人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11568

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

公开(公告)号：US07732276B2

公开(公告)日：2010-06-08

申请号：US11796582

申请日：2007-04-26

申请人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

发明人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/11568

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

公开(公告)号：US07985674B2

公开(公告)日：2011-07-26

申请号：US12290916

申请日：2008-11-05

申请人： Sung Jin Kim ,  Alexander Nickel ,  Minh-Van Ngo ,  Hieu Trung Pham ,  Masato Tsuboi ,  Shinich Imada

发明人： Sung Jin Kim ,  Alexander Nickel ,  Minh-Van Ngo ,  Hieu Trung Pham ,  Masato Tsuboi ,  Shinich Imada

IPC分类号： H01L21/4763

CPC分类号： H01L21/3185 ,  H01L21/02074 ,  H01L21/28282 ,  H01L29/792

摘要： Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH4) flow, reducing the overall exposure of the structure to hydrogen radicals. This results in the silicon nitride being strongly bonded to the structure and in improved performance.

摘要翻译： 在结构上沉积氮化硅（SiN）层之前，进行非等离子体增强操作，其中结构暴露于硅烷（SiH 4）流，从而减少了结构对氢自由基的总体暴露。 这导致氮化硅牢固地结合到结构上并且具有改进的性能。

公开(公告)号：US20080265301A1

公开(公告)日：2008-10-30

申请号：US11796582

申请日：2007-04-26

申请人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillips Jones ,  Mark Chang ,  Minh-Van Ngo

发明人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillips Jones ,  Mark Chang ,  Minh-Van Ngo

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L21/28282 ,  H01L27/11568

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

公开(公告)号：US08017870B2

公开(公告)日：2011-09-13

申请号：US12302087

申请日：2007-07-13

申请人： Keiji Kawakami ,  Alexander Nickel

发明人： Keiji Kawakami ,  Alexander Nickel

IPC分类号： H02G3/00

CPC分类号： B60R16/0222 ,  H02G3/0475 ,  Y10T16/063

摘要： A fastening device for a line, in particular for an electric cable (12) in a motor vehicle, is proposed, the fastening device having a bush (10) which can be locked in a holder (18), at least partially surrounds the line, is made of elastically deformable material and is fastened releaseably in a cutout (16) of the holder (18) by means of a contour (14). According to the invention, the surface of a bush (10), which is injection-moulded from plastic, is of segmented design in order to obtain easier deformability of the bush when fitting it into an associated holder (18).

摘要翻译： 提出了一种用于线路的紧固装置，特别是用于机动车辆中的电缆（12）的紧固装置，所述紧固装置具有可锁定在保持器（18）中的衬套（10），至少部分地围绕线 由弹性变形材料制成，并且通过轮廓（14）可释放地固定在保持器（18）的切口（16）中。 根据本发明，由塑料注射成型的衬套（10）的表面是分段设计的，以便在将衬套安装到相关联的保持器（18）中时更容易地变形。

公开(公告)号：US20090242235A1

公开(公告)日：2009-10-01

申请号：US12302087

申请日：2007-07-13

申请人： Keiji Kawakami ,  Alexander Nickel

发明人： Keiji Kawakami ,  Alexander Nickel

IPC分类号： H02G3/00 ,  B60R16/02

CPC分类号： B60R16/0222 ,  H02G3/0475 ,  Y10T16/063

摘要： A fastening device for a line, in particular for an electric cable (12) in a motor vehicle, is proposed, the fastening device having a bush (10) which can be locked in a holder (18), at least partially surrounds the line, is made of elastically deformable material and is fastened releaseably in a cutout (16) of the holder (18) by means of a contour (14). According to the invention, the surface of a bush (10), which is injection-moulded from plastic, is of segmented design in order to obtain easier deformability of the bush when fitting it into an associated holder (18).

摘要翻译： 提出了一种用于线路的紧固装置，特别是用于机动车辆中的电缆（12）的紧固装置，所述紧固装置具有可锁定在保持器（18）中的衬套（10），至少部分地围绕线 由弹性变形材料制成，并且通过轮廓（14）可释放地固定在保持器（18）的切口（16）中。 根据本发明，由塑料注射成型的衬套（10）的表面是分段设计的，以便在将衬套安装到相关联的保持器（18）中时更容易地变形。

公开(公告)号：US08384146B2

公开(公告)日：2013-02-26

申请号：US13428848

申请日：2012-03-23

申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US08202779B2

公开(公告)日：2012-06-19

申请号：US12891310

申请日：2010-09-27

申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US07776682B1

公开(公告)日：2010-08-17

申请号：US11110165

申请日：2005-04-20

申请人： Alexander Nickel ,  Suzette K. Pangrle ,  Steven C. Avanzino ,  Jeffrey Shields ,  Fei Wang ,  Minh Tran ,  Juri H. Krieger ,  Igor Sokolik

发明人： Alexander Nickel ,  Suzette K. Pangrle ,  Steven C. Avanzino ,  Jeffrey Shields ,  Fei Wang ,  Minh Tran ,  Juri H. Krieger ,  Igor Sokolik

IPC分类号： H01L21/8242

CPC分类号： H01L45/1233 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/141 ,  H01L45/142 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

摘要： Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.

摘要翻译： 公开了用于改善记忆单元中电性能的细胞间细胞重复性的方法和系统。 所述方法包括在无源层上形成具有有序孔隙率的非导电材料。 有序孔隙度可以促进导电通道的形成，电荷载体可以穿过导​​电通道迁移穿过另外的非导电层以便于改变存储器单元的状态。 可以可选地在非导电层上形成阻挡层，并且可以以基本上垂直于导电沟道的方式定向排序的孔隙，使得穿过非导电层迁移的电荷不能渗透到阻挡层。 该方法提供了具有成本效益和电可靠性的存储单元的微电子器件的制造。