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公开(公告)号：US20060224862A1
公开(公告)日：2006-10-05
申请号：US11093375
申请日：2005-03-29
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
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公开(公告)号：US20080091867A1
公开(公告)日：2008-04-17
申请号：US11954615
申请日：2007-12-12
IPC分类号： G06F9/26
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译： 公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。 定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。 所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。
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13.发明申请Pointer computation method and system for a scalable, programmable circular buffer 审中-公开指针计算方法和系统，用于可扩展的可编程循环缓冲区公开(公告)号：US20070094478A1
公开(公告)日：2007-04-26
申请号：US11255434
申请日：2005-10-20
申请人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , Mao Zeng , Sujat Jamil , William Anderson
发明人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , Mao Zeng , Sujat Jamil , William Anderson
IPC分类号： G06F12/00
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译： 用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定 大于长度。 该方法和系统确定循环缓冲器中的地址的当前指针位置，起始地址和结束地址之间的位的步幅值，循环缓冲器内的新指针位置，其从当前指针位置移位数字 的步幅值。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。
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14.发明申请System and method of executing program threads in a multi-threaded processor 有权在多线程处理器中执行程序线程的系统和方法公开(公告)号：US20060242645A1
公开(公告)日：2006-10-26
申请号：US11115917
申请日：2005-04-26
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。
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公开(公告)号：US20060218373A1
公开(公告)日：2006-09-28
申请号：US11089619
申请日：2005-03-24
IPC分类号： G06F9/34
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。
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16.发明授权Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权为交错多线程环境中的数字信号处理器注册文件公开(公告)号：US08713286B2
公开(公告)日：2014-04-29
申请号：US11115916
申请日：2005-04-26
IPC分类号： G06F7/57
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。
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17.发明授权Method and system for variable thread allocation and switching in a multithreaded processor 有权多线程处理器中可变线程分配和切换的方法和系统公开(公告)号：US07917907B2
公开(公告)日：2011-03-29
申请号：US11089474
申请日：2005-03-23
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。
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公开(公告)号：US07685411B2
公开(公告)日：2010-03-23
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译： 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。
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19.发明申请Method and system to indicate an exception-triggering page within a microprocessor 有权用于指示微处理器内的异常触发页面的方法和系统公开(公告)号：US20080016316A1
公开(公告)日：2008-01-17
申请号：US11487284
申请日：2006-07-14
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.
摘要翻译： 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。
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20.发明授权Mixed superscalar and VLIW instruction issuing and processing method and system 有权混合超标量和VLIW指令发布和处理方法和系统公开(公告)号：US07590824B2
公开(公告)日：2009-09-15
申请号：US11093375
申请日：2005-03-29
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。 多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。 该系列可执行指令通过各种指令依赖关联。 该方法和系统进一步标识列出多个并行可执行指令的混合指令。 一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。 然后，根据所述各种指令依赖性，串行执行指令被串行执行。
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