Integrated transceiver with lightpipe coupler

    公开(公告)号:US10128954B2

    公开(公告)日:2018-11-13

    申请号:US15900357

    申请日:2018-02-20

    Applicant: Luxtera, Inc.

    Abstract: A transceiver comprising a chip, a semiconductor laser, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via a light pipe with a sloped reflective surface coupled to the chip, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip. The light pipe may be a planar lightwave circuit (PLC).

    COUPLING OPTICAL SIGNALS INTO SILICON OPTOELECTRONIC CHIPS
    14.
    发明申请
    COUPLING OPTICAL SIGNALS INTO SILICON OPTOELECTRONIC CHIPS 有权
    将光信号耦合到硅光电子芯片中

    公开(公告)号:US20150028192A1

    公开(公告)日:2015-01-29

    申请号:US14513886

    申请日:2014-10-14

    Applicant: Luxtera, Inc.

    Abstract: A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of a CMOS photonic chip in a photonic transceiver, wherein photonic, electronic, or optoelectronic devices may be integrated in layers on a front surface of the CMOS photonic chip. Optical couplers, such as grating couplers, may receive the optical signals in the front surface. The optical signals may be coupled into the back surface of the chips via optical fibers and/or optical source assemblies. The optical signals may be coupled to the optical couplers via a light path etched in the chips, which may be refilled with silicon dioxide. The chips may be bonded to a second chip. Optical signals may be reflected back to the optical couplers via metal reflectors, which may be integrated in dielectric layers on the chips.

    Abstract translation: 公开了一种用于将光信号耦合到硅光电芯片的方法和系统,并且可以包括将一个或多个光信号耦合到光子收发器中的CMOS光子芯片的背表面,其中光子,电子或光电器件可以集成在层 在CMOS光子芯片的正面上。 诸如光栅耦合器的光耦合器可以在前表面中接收光信号。 光信号可以经由光纤和/或光源组件耦合到芯片的后表面中。 光信号可以经由在芯片中蚀刻的光路耦合到光耦合器,其可以用二氧化硅再填充。 芯片可以结合到第二芯片。 光信号可以经由金属反射器反射回到光耦合器,金属反射器可以集成在芯片上的电介质层中。

    Method and system for optoelectronics transceivers integrated on a CMOS chip

    公开(公告)号:US10341021B2

    公开(公告)日:2019-07-02

    申请号:US15804680

    申请日:2017-11-06

    Applicant: Luxtera, Inc.

    Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via optical couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

    Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

    公开(公告)号:US10061094B2

    公开(公告)日:2018-08-28

    申请号:US15716103

    申请日:2017-09-26

    Applicant: Luxtera, Inc.

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

    Method And System For Implementing High-Speed Electrical Interfaces Between Semiconductor Dies in Optical Communication Systems

    公开(公告)号:US20180017747A1

    公开(公告)日:2018-01-18

    申请号:US15716103

    申请日:2017-09-26

    Applicant: Luxtera, Inc.

    CPC classification number: G02B6/4274 G02B6/4286

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Patent Agency Ranking