公开(公告)号：US20210335804A1

公开(公告)日：2021-10-28

申请号：US16857226

申请日：2020-04-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first staircase structure, a second staircase structure, a conductive pillar, and a contact pillar. The first staircase structure includes conductive stair layers. The conductive pillar passes through the second staircase structure. The conductive pillar has an upper conductive pillar end and a lower conductive pillar end opposing to the upper conductive pillar end. The contact pillar is electrically connected on one conductive stair layer of the conductive stair layers. The contact pillar has an upper contact end and a lower contact end opposing to the upper contact end. The upper contact end and the lower contact end are respectively electrically connected to the upper conductive pillar end of the conductive pillar and the one conductive stair layer.

公开(公告)号：US20200258898A1

公开(公告)日：2020-08-13

申请号：US16273301

申请日：2019-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH ,  Yu-Wei JIANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

公开(公告)号：US20160086971A1

公开(公告)日：2016-03-24

申请号：US14948482

申请日：2015-11-23

Applicant: Macronix International Co., Ltd

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Yen-Hao SHIH

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.