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公开(公告)号：US20210342094A1
公开(公告)日：2021-11-04
申请号：US16863202
申请日：2020-04-30
Applicant: Macronix International Co., Ltd.
Inventor： Ting-Yu Liu , Yi-Chun Liu
IPC: G06F3/06 , G06F12/10 , G06F12/123
Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.
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公开(公告)号：US10915442B2
公开(公告)日：2021-02-09
申请号：US16572922
申请日：2019-09-17
Applicant: Macronix International Co., Ltd.
Inventor： Ting-Yu Liu
Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.
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公开(公告)号：US20180373655A1
公开(公告)日：2018-12-27
申请号：US15630075
申请日：2017-06-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ting-Yu Liu
Abstract: A controller for a memory system is disclosed. The controller includes logic configured to execute host requests and memory management operations. The memory management operations have a plurality of memory command cycles. The logic is configured to suspend the memory management operation upon completion of a memory command cycle in the plurality of memory command cycles before a final stage when a host read request is received during execution of the memory management operation, and configured to continue the memory management operation when a host request other than a read request is received during execution of the memory management operation.
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公开(公告)号：US20180165219A1
公开(公告)日：2018-06-14
申请号：US15375545
申请日：2016-12-12
Applicant: Macronix International Co., Ltd.
Inventor： Tzu-Yi Yang , Ting-Yu Liu , Yi-Chun Liu
IPC: G06F12/121 , G06F3/06
CPC classification number: G06F3/065 , G06F3/0619 , G06F3/068 , G06F12/0638 , G06F2212/1016
Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.
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公开(公告)号：US20230214158A1
公开(公告)日：2023-07-06
申请号：US18175726
申请日：2023-02-28
Applicant: Macronix International Co., Ltd.
Inventor： Ting-Yu Liu , Yi-Chun Liu
IPC: G06F3/06 , G06F12/123 , G06F12/10
CPC classification number: G06F3/0659 , G06F3/0604 , G06F12/124 , G06F12/10 , G06F3/0674
Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.
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Patent Agency Ranking
公开(公告)号：US20230054801A1
公开(公告)日：2023-02-23
申请号：US17408177
申请日：2021-08-20
Applicant: MACRONIX International Co., Ltd.
Inventor： Chang-Hao Chen , Ting-Yu Liu
IPC: G06F3/06 , G06F12/0804 , G06F12/1009
Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.
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公开(公告)号：US10521375B2
公开(公告)日：2019-12-31
申请号：US15630075
申请日：2017-06-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ting-Yu Liu
Abstract: A controller for a memory system is disclosed. The controller includes logic configured to execute host requests and memory management operations. The memory management operations have a plurality of memory command cycles. The logic is configured to suspend the memory management operation upon completion of a memory command cycle in the plurality of memory command cycles before a final stage when a host read request is received during execution of the memory management operation, and configured to continue the memory management operation when a host request other than a read request is received during execution of the memory management operation.
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公开(公告)号：US10445230B2
公开(公告)日：2019-10-15
申请号：US15836476
申请日：2017-12-08
Applicant: Macronix International Co., Ltd.
Inventor： Ting-Yu Liu
Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes.
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公开(公告)号：US20190179698A1
公开(公告)日：2019-06-13
申请号：US15835859
申请日：2017-12-08
Applicant: Macronix International Co., Ltd.
Inventor： Ting-Yu Liu , Yi-Chun Liu
CPC classification number: G06F11/1048 , G06F3/064 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7208
Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.
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公开(公告)号：US10007446B2
公开(公告)日：2018-06-26
申请号：US14703941
申请日：2015-05-05
Applicant: Macronix International Co., Ltd.
Inventor： Wei-Chieh Huang , Li-Chun Huang , Yu-Ming Chang , Hung-Sheng Chang , Hsiang-Pang Li , Ting-Yu Liu , Chien-Hsin Liu , Nai-Ping Kuo
CPC classification number: G06F3/067 , G06F3/061 , G06F3/064 , G06F3/0656 , G06F3/0679 , G06F12/0238 , G06F2212/1024 , G06F2212/7201 , G06F2212/7203
Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.
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