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    MEMORY ORPRATING METHOD AND MEMORY DEVICE USING THE SAME
    3.
    发明申请
    MEMORY ORPRATING METHOD AND MEMORY DEVICE USING THE SAME 有权
    使用该存储器的记录方法和存储器件

    公开(公告)号：US20160147464A1

    公开(公告)日：2016-05-26

    申请号：US14805498

    申请日：2015-07-22

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC分类号： G06F3/06

    CPC分类号： G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

    摘要： An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

    摘要翻译： 一种用于存储器的操作方法，所述存储器包括至少一个存储块，所述至少一个存储块包括与所述第一页对应的多个第一页和多个第二页，所述操作方法包括以下步骤：确定所述第一页的目标第一页 页面是有效的，其中目标第一页面对应于第二页面的目标第二页面; 如果目标第一页有效，则在目标第二页上执行第一类型编程; 如果目标第一页无效，则在目标第二页上执行第二类型编程。

    Data management method for memory and memory apparatus
    4.
    发明授权
    Data management method for memory and memory apparatus 有权

    公开(公告)号：US10445008B2

    公开(公告)日：2019-10-15

    申请号：US15705309

    申请日：2017-09-15

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yung-Chun Li ,  Ping-Hsien Lin ,  Yu-Ming Chang

    IPC分类号： G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F13/00 ,  G06F13/28

    摘要： A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.

    Memory system and memory management method thereof
    5.
    发明授权
    Memory system and memory management method thereof 有权

    公开(公告)号：US10108555B2

    公开(公告)日：2018-10-23

    申请号：US15370059

    申请日：2016-12-06

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Ming Chang ,  Yuan-Hao Chang ,  Hsiu-Chang Chen ,  Tei-Wei Kuo

    IPC分类号： G06F12/02 ,  G06F12/121 ,  G06F12/00 ,  G06F12/06 ,  G06F12/1009

    摘要： A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type memory; allocating a page from the first type memory according to a system request, and inserting the page into the inactive list accordingly; moving the page from the inactive list to the write active list or the read active list in response to two or more successive access operations on the page; and referring the page to a physical address on the second type memory when the page is in the write active list.

    Half block management for flash storage devices
    8.
    发明授权
    Half block management for flash storage devices 有权
    闪存存储设备的半块管理

    公开(公告)号：US09558108B2

    公开(公告)日：2017-01-31

    申请号：US14018149

    申请日：2013-09-04

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16

    CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

    摘要： A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

    摘要翻译： 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。

    MEMORY DEVICE AND ASSOCIATED ERASE METHOD
    9.
    发明申请
    MEMORY DEVICE AND ASSOCIATED ERASE METHOD 有权
    存储器件和相关的擦除方法

    公开(公告)号：US20160300617A1

    公开(公告)日：2016-10-13

    申请号：US14684561

    申请日：2015-04-13

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hung-Sheng Chang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/18

    摘要： A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

    摘要翻译： 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。

    Memory device and associated erase method
    10.
    发明授权
    Memory device and associated erase method 有权
    存储器和相关的擦除方法

    公开(公告)号：US09466384B1

    公开(公告)日：2016-10-11

    申请号：US14684561

    申请日：2015-04-13

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hung-Sheng Chang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

    IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/18 ,  G11C16/14

    CPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/18

    摘要： A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

    摘要翻译： 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。