公开(公告)号：US12142633B2

公开(公告)日：2024-11-12

申请号：US18332863

申请日：2023-06-12

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US20220357211A1

公开(公告)日：2022-11-10

申请号：US17719387

申请日：2022-04-13

Applicant: MEDIATEK INC.

Inventor： Min-Hang Hsieh ,  Jyun-Jia Huang ,  Chien-Sheng Chao ,  Ghien-An Shih ,  Ching-Chung Ko ,  Yu-Cheng Su ,  Lin-Chien Chen ,  Ai-Yun Liu ,  Chia-Hsin Hu

IPC: G01K7/01

Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.

公开(公告)号：US11367788B2

公开(公告)日：2022-06-21

申请号：US16853889

申请日：2020-04-21

Applicant: MEDIATEK INC.

Inventor： Jing-Chyi Liao ,  Ching-Chung Ko ,  Zheng Zeng

IPC: H01L29/78

Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.

公开(公告)号：US09893049B2

公开(公告)日：2018-02-13

申请号：US14630733

申请日：2015-02-25

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Bo-Shih Huang

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/47 ,  H01L29/872 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.

公开(公告)号：US20140124871A1

公开(公告)日：2014-05-08

申请号：US14161611

申请日：2014-01-22

Applicant: MEDIATEK INC.

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。