公开(公告)号：US20150249060A1

公开(公告)日：2015-09-03

申请号：US14714331

申请日：2015-05-17

Applicant: Mediatek Inc.

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract translation: 倒装芯片封装包括：耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱的一部分突出于所述通孔开口。

公开(公告)号：US20200294948A1

公开(公告)日：2020-09-17

申请号：US16888845

申请日：2020-05-31

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/498

Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.

公开(公告)号：US09659893B2

公开(公告)日：2017-05-23

申请号：US14826471

申请日：2015-08-14

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/50

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/183 ,  H01L2924/35 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.