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    SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY
    11.
    发明申请
    SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY 有权

    公开(公告)号：US20220181228A1

    公开(公告)日：2022-06-09

    申请号：US17512665

    申请日：2021-10-27

    Applicant: MEDIATEK INC.

    Inventor： Tien-Chang Chang ,  Yan-Liang Ji

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.

    MOS device with isolated drain and method for fabricating the same
    13.
    发明授权
    MOS device with isolated drain and method for fabricating the same 有权
    具有隔离漏极的MOS器件及其制造方法

    公开(公告)号：US09006825B1

    公开(公告)日：2015-04-14

    申请号：US14039161

    申请日：2013-09-27

    Applicant: MediaTek Inc.

    Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

    Abstract translation: 具有隔离漏极的MOS器件包括：具有第一导电类型的半导体衬底; 嵌入在半导体衬底的第一部分中的第一阱区，具有第二导电类型; 第二阱区，设置在所述半导体衬底的第二部分中，覆盖所述第一阱区并且具有所述第一导电类型; 设置在半导体衬底的第三部分中的第三阱区，覆盖具有第二导电类型的第一阱区; 第四阱区，设置在具有第一导电类型的第一和第三阱区之间的半导体衬底的第四部分中; 形成在半导体衬底上的栅叠层; 源区域，其设置在所述第二阱区域的具有所述第二导电类型的部分中; 以及设置在具有第二导电类型的第四阱区域的一部分中的漏极区域。

    Semiconductor package and manufacturing method thereof
    15.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US11935852B2

    公开(公告)日：2024-03-19

    申请号：US17580699

    申请日：2022-01-21

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang Ji

    IPC: H01L23/00

    CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05094 ,  H01L2224/13026

    Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

    Semiconductor device capable of high-voltage operation
    16.
    发明授权
    Semiconductor device capable of high-voltage operation 有权

    公开(公告)号：US10396166B2

    公开(公告)日：2019-08-27

    申请号：US15425207

    申请日：2017-02-06

    Applicant: MEDIATEK INC.

    Inventor： Cheng Hua Lin ,  Yan-Liang Ji

    IPC: H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

    Semiconductor device capable of high-voltage operation
    17.
    发明授权
    Semiconductor device capable of high-voltage operation 有权

    公开(公告)号：US10199496B2

    公开(公告)日：2019-02-05

    申请号：US15411099

    申请日：2017-01-20

    Applicant: MEDIATEK INC.

    Inventor： Cheng-Hua Lin ,  Yan-Liang Ji ,  Chih-Wen Hsiung

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L27/06 ,  H01L49/02

    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

    Electronic component and manufacturing method thereof
    18.
    发明授权
    Electronic component and manufacturing method thereof 有权

    公开(公告)号：US10177225B2

    公开(公告)日：2019-01-08

    申请号：US15206399

    申请日：2016-07-11

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Puo-Yu Chiang

    IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/535 ,  H01L29/36 ,  H01L29/423

    Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

    MOS device with isolated drain and method for fabricating the same
    20.
    发明授权
    MOS device with isolated drain and method for fabricating the same 有权
    具有隔离漏极的MOS器件及其制造方法

    公开(公告)号：US09029223B1

    公开(公告)日：2015-05-12

    申请号：US14582608

    申请日：2014-12-24

    Applicant: MediaTek Inc.

    Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/266 ,  H01L29/06

    CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device with isolated drain. The method performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate, exposing portions of the semiconductor substrate; performing a first ion implant process on the portions of the semiconductor substrate exposed by the first patterned mask layer; performing a second ion implant process to a second well region exposed, forming a fourth well region between the first well region and the second well region; performing a third implant process to the second well region, forming a fifth well region overlying the fourth well region; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

    Abstract translation: 一种用于制造具有隔离漏极的金属氧化物半导体（MOS）器件的方法。 该方法执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层，暴露所述半导体衬底的部分; 在由第一图案化掩模层曝光的半导体衬底的部分上执行第一离子注入工艺; 对暴露的第二阱区域执行第二离子注入工艺，在第一阱区域和第二阱区域之间形成第四阱区域; 对所述第二阱区域执行第三注入工艺，形成覆盖所述第四阱区域的第五阱区域; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

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