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    Look-ahead handling of page faults in I/O operations
    11.
    发明授权
    Look-ahead handling of page faults in I/O operations 有权
    在I / O操作中提前处理页面错误

    公开(公告)号：US08914458B2

    公开(公告)日：2014-12-16

    申请号：US13628075

    申请日：2012-09-27

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shachar Raindel ,  Haggai Eran ,  Liran Liss ,  Noam Bloch

    IPC: G06F15/167

    CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0659

    Abstract: A method for data transfer includes receiving in an input/output (I/O) operation a first segment of data to be written to a specified virtual address in a host memory. Upon receiving the first segment of the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. At least one second page of the host memory is identified, to which a second segment of the data is expected to be written. Responsively to detecting that the first page is swapped out and to identifying the at least one second page, at least the first and second pages are swapped into the host memory. After swapping at least the first and second pages into the host memory, the data are written to the first and second pages.

    Abstract translation: 一种用于数据传输的方法包括在输入/输出（I / O）操作中接收要写入主机存储器中的指定虚拟地址的第一数据段。 在接收到数据的第一段时，检测到包含指定虚拟地址的第一页被转换出主机存储器。 标识主机存储器的至少一个第二页，期望数据的第二段被写入到其上。 响应于检测到第一页面被换出并且识别至少一个第二页面，至少第一页面和第二页面被交换到主机存储器中。 至少将第一页和第二页交换到主机存储器之后，数据被写入第一页和第二页。

    Use of free pages in handling of page faults
    12.
    发明申请
    Use of free pages in handling of page faults 有权
    在处理页面错误时使用免费页面

    公开(公告)号：US20140089528A1

    公开(公告)日：2014-03-27

    申请号：US13628187

    申请日：2012-09-27

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Noam Bloch ,  Shachar Raindel ,  Haggai Eran ,  Liran Liss

    IPC: G06F3/00

    CPC classification number: H04L49/9089 ,  G06F12/08 ,  H04L69/321

    Abstract: A method for data transfer includes receiving in an input/output (I/O) operation data to be written to a specified virtual address in a host memory. Upon receiving the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. Responsively to detecting that the first page is swapped out, the received data are written to a second, free page in the host memory, and the specified virtual address is remapped to the free page.

    Abstract translation: 一种用于数据传输的方法包括在主机存储器中接收要写入指定虚拟地址的输入/输出（I / O）操作数据。 在接收到数据时，检测到包含指定的虚拟地址的第一页被转换出主机存储器。 响应于检测到第一页被换出，所接收的数据被写入主机存储器中的第二个空闲页面，并且将指定的虚拟地址重新映射到空闲页面。

    Computational accelerator for packet payload operations
    16.
    发明授权
    Computational accelerator for packet payload operations 有权

    公开(公告)号：US11005771B2

    公开(公告)日：2021-05-11

    申请号：US16159767

    申请日：2018-10-15

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

    IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08 ,  H04L12/851 ,  H04L12/00 ,  H04L12/413

    Abstract: Packet processing apparatus includes a first interface coupled to a host processor and a second interface configured to transmit and receive data packets to and from a packet communication network. A memory holds context information with respect to one or more flows of the data packets conveyed between the host processor and the network in accordance with a reliable transport protocol and with respect to encoding, in accordance with a session-layer protocol, of data records that are conveyed in the payloads of the data packets in the one or more flows. Processing circuitry, coupled between the first and second interfaces, transmits and receives the data packets and includes acceleration logic, which encodes and decodes the data records in accordance with the session-layer protocol using the context information while updating the context information in accordance with the serial numbers and the data records of the transmitted data packets.

    Zero-copy processing
    20.
    发明授权
    Zero-copy processing 有权

    公开(公告)号：US11757796B2

    公开(公告)日：2023-09-12

    申请号：US17488362

    申请日：2021-09-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Haggai Eran ,  Liran Liss ,  Yuval Shpigelman ,  Idan Burstein

    IPC: H04L61/00 ,  H04L49/00 ,  H04L12/40 ,  H04L49/90

    CPC classification number: H04L49/3072 ,  H04L12/40071 ,  H04L49/9042

    Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

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