公开(公告)号：US09343184B2

公开(公告)日：2016-05-17

申请号：US14246589

申请日：2014-04-07

Applicant: Micron Technology, Inc.

Inventor： Alan J. Wilson ,  Jeffrey Wright

IPC: G11C7/00 ,  G11C29/00 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C11/408 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C7/24 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/70 ,  G11C29/789 ,  G11C29/806 ,  G11C29/838 ,  G11C2029/4402

Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

Abstract translation: 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的缺陷地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。

公开(公告)号：US09202595B2

公开(公告)日：2015-12-01

申请号：US14077630

申请日：2013-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Alan J. Wilson ,  Jeffrey Wright

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G11C29/76 ,  G11C8/06 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: An apparatus for post package repair can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells.

Abstract translation: 用于邮包修复的装置可以包括包装中的存储器单元。 存储元件可以存储响应于被激活的封装后修复模式的信息。 信息可以标识映射到要修复的存储器单元的一部分的地址。 存储元件可以响应于从包的节点接收的数据来存储信息。 行走令牌电路可以响应于被激活的封装后修复模式，以串行方式询问存储在存储元件中的信息。 映射电路可以根据询问将要修复的地址重新映射到存储器单元的另一部分。

公开(公告)号：US20250085867A1

公开(公告)日：2025-03-13

申请号：US18955719

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US20250044957A1

公开(公告)日：2025-02-06

申请号：US18804609

申请日：2024-08-14

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

公开(公告)号：US12159039B2

公开(公告)日：2024-12-03

申请号：US17731100

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US20240362114A1

公开(公告)日：2024-10-31

申请号：US18607152

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim ,  Donald M. Morgan ,  Alan J. Wilson

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.

公开(公告)号：US12086425B2

公开(公告)日：2024-09-10

申请号：US17730755

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

公开(公告)号：US20210335443A1

公开(公告)日：2021-10-28

申请号：US17317221

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Alan J. Wilson

IPC: G11C29/44 ,  G11C16/10 ,  G11C16/08

Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.

公开(公告)号：US11145387B2

公开(公告)日：2021-10-12

申请号：US17062264

申请日：2020-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Alan J. Wilson

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/32 ,  G11C17/18 ,  G11C11/408 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C29/44

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

公开(公告)号：US11011250B2

公开(公告)日：2021-05-18

申请号：US16805049

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Alan J. Wilson

IPC: G11C17/00 ,  G11C29/44 ,  G11C16/10 ,  G11C16/08

Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.