公开(公告)号：US20220188253A1

公开(公告)日：2022-06-16

申请号：US17685212

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  H01L23/538 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20220121609A1

公开(公告)日：2022-04-21

申请号：US17562550

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F13/42 ,  G06F15/167

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

公开(公告)号：US20210191622A1

公开(公告)日：2021-06-24

申请号：US16951299

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

公开(公告)号：US10998291B2

公开(公告)日：2021-05-04

申请号：US16298338

申请日：2019-03-11

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  G11C5/10 ,  G11C29/12

Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.

公开(公告)号：US10768831B2

公开(公告)日：2020-09-08

申请号：US16235407

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F3/06 ,  G06F21/62

Abstract: Apparatuses and methods related to implementing a non-persistent unlock state for secure memory. Implementing the non-persistent unlock state can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated following the placement of the protected region in a non-persistent unlocked mode. If the row of the memory array corresponding to the access command is activated, then the protected region can be placed on a locked mode.

公开(公告)号：US10741468B2

公开(公告)日：2020-08-11

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10714150B2

公开(公告)日：2020-07-14

申请号：US16279590

申请日：2019-02-19

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02 ,  H01L25/18 ,  G11C11/4063

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US20200210078A1

公开(公告)日：2020-07-02

申请号：US16235482

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F3/06

Abstract: Apparatuses and methods related to tracking unauthorized access commands for memory. Identifying unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then an access count can be incremented to signify the unauthorized access command.

公开(公告)号：US20200159687A1

公开(公告)日：2020-05-21

申请号：US16773784

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F13/42 ,  G06F15/167

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

公开(公告)号：US20190179769A1

公开(公告)日：2019-06-13

申请号：US16058868

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F12/1027 ,  G06F3/06

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.